4524_M Datasheet, PDF (246/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.9 Power down
(3) Clock control register MR
Table 2.9.6 shows the clock control register MR.
Set the contents of this register through register A with the TMRA instruction.
The contents of register MR is transferred to register A with the TAMR instruction.
Table 2.9.6 Clock control register MR
Clock control register MR
at reset : 11002 at power down : state retained
MR3
MR2
Operation mode selection bits
MR3 MR2
Operation mode
0 0 Through-mode (frequency not divided)
0 1 Frequency divided by 2 mode
1 0 Frequency divided by 4 mode
MR1
Main clock oscillation circuit
control bit
11
0
1
Frequency divided by 8 mode
Main clock oscillation enabled
Main clock oscillation stop
MR0 ^{System clock selection bit}
0 Main clock (f(XIN) or f(RING))
1 Sub-clock (f(XCIN))
Note: “R” represents read enabled, and “W” represents write enabled.
(4) Pull-up control register PU0
Table 2.9.7 shows the pull-up control register PU0.
Set the contents of this register through register A with the TPU0A instruction.
The contents of register PU0 is transferred to register A with the TAPU0 instruction.
Table 2.9.7 Pull-up control register PU0
Pull-up control register PU0
at reset : 00002 at power down : state retained
Port P03
PU03
pull-up transistor control bit
0 Pull-up transistor OFF
1 Pull-up transistor ON
Port P02
PU02
pull-up transistor control bit
0 Pull-up transistor OFF
1 Pull-up transistor ON
Port P01
PU01
pull-up transistor control bit
0 Pull-up transistor OFF
1 Pull-up transistor ON
Port P00
PU00
pull-up transistor control bit
0 Pull-up transistor OFF
1 Pull-up transistor ON
Note: “R” represents read enabled, and “W” represents write enabled.
R/W
R/W
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-82