4524_M Datasheet, PDF (181/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.2 Interrupts
(4) Timer 2 interrupt
The interrupt request occurs by the timer 2 underflow.
s Timer 2 interrupt processing
q When the interrupt is used
The interrupt occurrence is enabled when the bit 3 of the interrupt control register V1 and the
interrupt enable flag INTE are set to “1.” When the timer 2 interrupt occurs, the interrupt processing
is executed from address 6 in page 1.
q When the interrupt is not used
The interrupt is disabled and the SNZT2 instruction is valid when the bit 3 of register V1 is set
to “0.”
(5) Timer 3 interrupt
The interrupt request occurs by the timer 3 underflow.
s Timer 3 interrupt processing
q When the interrupt is used
The interrupt occurrence is enabled when the bit 0 of the interrupt control register V2 and the
interrupt enable flag INTE are set to “1.” When the timer 3 interrupt occurs, the interrupt processing
is executed from address 8 in page 1.
q When the interrupt is not used
The interrupt is disabled and the SNZT3 instruction is valid when the bit 0 of register V2 is set
to “0.”
(6) Timer 5 interrupt
The interrupt request occurs by the timer 5 underflow.
s Timer 5 interrupt processing
q When the interrupt is used
The interrupt occurrence is enabled when the bit 1 of the interrupt control register V2 and the
interrupt enable flag INTE are set to “1.” When the timer 5 interrupt occurs, the interrupt processing
is executed from address A in page 1.
q When the interrupt is not used
The interrupt is disabled and the SNZT5 instruction is valid when the bit 1 of register V2 is set
to “0.”
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-17