4524_M Datasheet, PDF (228/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.5 Serial I/O
➀ Disable Interrupts
Timer 4 and serial I/O interrupt are temporarily disabled.
Interrupt enable flag INTE 0
All interrupts disabled [DI]
Interrupt control register V2
b3
b0
0 ✕ ✕ ✕ b3: Timer 4 and serial I/O interrupts occurrence disabled [TV2A]
↓
➁ Select Serial I/O Interrupt
Serial I/O is selected for the interrupt source.
Interrupt control register I3
b0
1 Serial I/O interrupt valid [TI3A]
↓
➂ Set Port
Port for control signal is set to “H” output.
Register Y
Port D3 output latch
b3
b0
0011
1
Specify bit position of port D [TYA]
Set to “H” output [SD]
b3
b0
Port output structure control register FR1 1 ✕ ✕ ✕ b3: Port D3 CMOS output selected
↓
➃ Set Serial I/O
Serial I/O control regsiter JI
b3
b0
1111
[TJ1A]
b3, b2: External clock is selected for synchronous clock
b1, b0: Serial I/O ports SCK, SOUT, SIN selected
↓
➄ Clear Interrupt Request
Serial I/O interrupt activated condition is cleared.
Serial I/O transmit/receive completion flag SIOF 0
Serial I/O interrupt activated condition cleared [SNZSI]
↓
( ) Note when the interrupt request is cleared
When ➄ is executed, considering the skip of the next instruction according to the flag SIOF,
insert the NOP instruction after the SNZSI instruction.
↓
➅ Set Interrupts
The Serial I/O interrupt which is temporarily disabled is enabled.
Interrupt control register V2
b3
b0
1 ✕ ✕ ✕ b3: Serial I/O interrupt occurrence enabled [TV2A]
Interrupt enable flag INTE 1
All interrupts enabled [EI]
↓
~ Set Transmit Data
Transmit data is set to serial I/O register.
Serial I/O register SI ✕✕16
[TSIAB]
↓
➇ Set Start of Serial I/O Operation
Serial I/O operation enabled state (serial transfer started, control signal “L” level output) is set.
Serial transfer start
[SST]
b3
b0
Register Y 0 0 1 1 Specify bit position of port D [TYA]
Port D3 output latch 0
Set to “L” output [RD]
:
↓
Serial transmit/receive by clock of master side
:
↓
➈ Receive Data Processing by Serial I/O interrupt
Serial I/O operation disabled state (control signal “H” level output) is set and received data processing is performed..
Register Y
Port D3 output latch
Register SI
b3
b0
0011
1
→
Specify bit position of port D [TYA]
Set to “H” output [SD]
register A, register B [TABSI]
↓
When serial communication is executed, repeat ~ to ➈.
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Fig. 2.5.6 Setting example when a serial I/O interrupt of slave side is used
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-64