4524_M Datasheet, PDF (227/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.5 Serial I/O
➀ Disable Interrupts (Note)
Timer 4 and serial I/O interrupt are temporarily disabled.
Interrupt enable flag INTE 0
All interrupts disabled [DI]
Interrupt control register V2
b3
b0
0 ✕ ✕ ✕ b3: Timer 4 and serial I/O interrupts occurrence disabled [TV2A]
↓
➁ Select Serial I/O Interrupt (Note)
Serial I/O is selected for the interrupt source.
Interrupt control register I3
b0
1 Serial I/O interrupt valid [TI3A]
↓
➂ Set Port
Port for control signal is set to input.
Register Y
Port D3 output latch
b3
00
1
b0
11
Specify bit position of port D [TYA]
Set to input [SD]
b3
b0
Port output structure control register FR1 0 ✕ ✕ ✕ b3: Port D3 N-channel open-drain output selected
↓
➃ Set Serial I/O
Serial I/O control regsiter JI
b3
b0
0111
[TJ1A]
b3, b2: Instruction clock divided by 4 is selected for
synchronous clock
b1, b0: Serial I/O ports SCK, SOUT, SIN selected
↓
➄ Clear Interrupt Request
Serial I/O interrupt activated condition is cleared.
Serial I/O transmit/receive completion flag SIOF 0
Serial I/O interrupt activated condition cleared [SNZSI]
↓
( ) Note when the interrupt request is cleared
When ➄ is executed, considering the skip of the next instruction according to the flag SIOF,
insert the NOP instruction after the SNZSI instruction.
↓
➅ Set Interrupts (Note)
Interrupts except serial I/O interrupt is enabled.
[EI]
↓
~ Set Transmit Data
Transmit data is set to serial I/O register.
Serial I/O register SI ✕✕16
[TSIAB]
↓
➇ Check Start Condition of Serial I/O Operation
Whether the transmit/receive of the slave side can be performed (pin level of control signal = “L”) or not is checked.
Register Y
Port D3 output latch
Port D3 input level check
b3
00
1
b0
11
Specify bit position of port D [TYA]
Set to input [SD]
[SZD]
↓
➈ Start Serial I/O Operation
If the transmit/receive of the slave side can be performed, serial transfer is started. [SST]
↓
➉ Check Serial I/O Interrupt Request
SIOF flag is checked. [SNZSI]
↓
11 Receive Data Processing
Data processing received by serial transfer is executed.
Register SI → register A, register B [TABSI]
↓
When serial communication is executed, repeat ~ to 11 .
Note: ➀, ➁ and ➅ are not required when timer 4 interrupt is used.
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Fig. 2.5.5 Setting example when a serial I/O of master side is not used
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
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