4524_M Datasheet, PDF (167/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.1 I/O pins
(3) Port P2
Port P2 is a 4-bit I/O port.
P20–P23 are also used as analog input pins AIN0–AIN3.
q Input
In the following condition, the pin state of port P2 is transferred as input data to register A when
the IAP2 instruction is executed.
• Set the output latch of specified port P2i (i=0, 1, 2 or 3) to “1” with the OP2A instruction.
If the output latch is “0”, “0” is output to specified port P2.
q Output
The contents of register A is set to the output latch with the OP2A instruction, and is output to port
P2.
The output structure is an N-channel open-drain.
Note: Ports P20–P23 are used as input/output port P2, set the corresponding bit of register Q2 to “0”.
(4) Port P3
Port P3 is a 4-bit I/O port.
P30–P33 are also used as analog input pins AIN4–AIN7.
q Input
In the following condition, the pin state of port P3 is transferred as input data to register A when
the IAP3 instruction is executed.
• Set the output latch of specified port P3i (i=0, 1, 2 or 3) to “1” with the OP3A instruction.
If the output latch is “0”, “0” is output to specified port P3.
q Output
The contents of register A is set to the output latch with the OP3A instruction, and is output to port
P3.
The output structure is an N-channel open-drain.
Note: Ports P30–P33 are used as input/output port P3, set the corresponding bit of register Q3 to “0”.
(5) Port P4
Port P4 is a 4-bit I/O port.
q Input
In the following conditions, the pin state of port P4 is transferred as input data to register A when
the IAP4 instruction is executed.
• Set bit i (i=0,1,2 or 3) of register FR3 to “0” according to the port to be used.
• Set the output latch of specified port P4i (i=0, 1, 2 or 3) to “1” with the OP4A instruction.
If FR3i is “0” and the output latch is “0”, “0” is output to specified port P4.
If FR3i is “1”, the output latch value is output to specified port P4.
q Output
The contents of register A is set to the output latch with the OP4A instruction, and is output to port
P4.
N-channel open-drain or CMOS can be selected as the output structure of port P4 in 1 bit unit by
setting register FR3.
Rev.2.00 Aug, 06 2004
2-3
REJ09B0107-0200Z