4524_M Datasheet, PDF (215/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.4 A/D converter
2.4.1 Related registers
(1) Interrupt control register V2
Table 2.4.1 shows the interrupt control register V2.
Set the contents of this register through register A with the TV2A instruction.
In addition, the TAV2 instruction can be used to transfer the contents of register V2 to register A.
Table 2.4.1 Interrupt control register V2
Interrupt control register V2
at reset : 00002
at power down : 00002
R/W
Timer 4, serial I/O interrupt 0 Interrupt disabled (SNZT4, SNZSI instruction is valid)
V23
enable bit (Note 2)
1 Interrupt enabled (SNZT4, SNZSI instruction is invalid) (Note 3)
V22 A/D interrupt enable bit
0 Interrupt disabled (SNZAD instruction is valid)
1 Interrupt enabled (SNZAD instruction is invalid) (Note 3)
V21 Timer 5 interrupt enable bit
0 Interrupt disabled (SNZT5 instruction is valid)
1 Interrupt enabled (SNZT5 instruction is invalid) (Note 3)
V20 Timer 3 interrupt enable bit
0 Interrupt disabled (SNZT3 instruction is valid)
1 Interrupt enabled (SNZT3 instruction is invalid) (Note 3)
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Select the timer 4 interrupt or serial I/O interrupt by the timer 4, serial I/O interrupt source
selection bit (I30).
3: These instructions are equivalent to the NOP instruction.
4: When setting the A/D converter, V23, V21 and V20 are not used.
(2) A/D control register Q1
Table 2.4.2 shows the A/D control register Q1.
Set the contents of this register through register A with the TQ1A instruction.
In addition, the TAQ1 instruction can be used to transfer the contents of register Q1 to register A.
Table 2.4.2 A/D control register Q1
A/D control register Q1
at reset : 00002 at power down : state retained
Q13 A/D operation mode control bit
0 A/D conversion mode
1 Comparator mode
Q12 Q11 Q10
Analog input pins
Q12
0 0 0 AIN0
0 0 1 AIN1
0 1 0 AIN2
Q11 Analog input pin selection bits 0 1 1 ^AIN3
1 0 0 AIN4
1 0 1 AIN5
Q10
1 1 0 AIN6
1 1 1 AIN7
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: In order to select AIN7–AIN0, set register Q1 after setting regsiter Q2, Q3.
R/W
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-51