4524_M Datasheet, PDF (245/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.9 Power down
2.9.2 Related registers
(1) Interrupt control register I1
Table 2.9.4 shows the interrupt control register I1.
Set the contents of this register through register A with the TI1A instruction.
In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A.
Table 2.9.4 Interrupt control register I1
Interrupt control register I1
at reset : 00002 at power down : state retained R/W
0 INT0 pin input disabled
I13 INT0 pin input control bit (Note 2)
1 INT0 pin input enabled
Falling waveform/“L” level (“L” level is recognized with
Interrupt valid waveform for INT0 0
the SNZI0 instruction)
I12 pin/return level selection bit
Rising waveform/“H” level (“H” level is recognized with
(Note 2)
1
the SNZI0 instruction)
INT0 pin edge detection circuit 0 One-sided edge detected
I11
control bit
1 Both edges detected
INT0 pin Timer 1 count start 0 Timer 1 count start synchronous circuit not selected
I10
synchronous circuit selection bit 1 Timer 1 count start synchronous circuit selected
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be
set. Accordingly, clear EXF0 flag with the SNZ0 instruction when the bit 0 (V10) of register V1 to
“0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is
performed with the SNZ0 instruction.
3: When setting the power down, I11–I10 are not used.
(2) Interrupt control register I2
Table 2.9.5 shows the interrupt control register I2.
Set the contents of this register through register A with the TI2A instruction.
In addition, the TAI2 instruction can be used to transfer the contents of register I2 to register A.
Table 2.9.5 Interrupt control register I2
Interrupt control register I2
at reset : 00002 at power down : state retained R/W
0 INT1 pin input disabled
I23 INT1 pin input control bit (Note 2)
1 INT1 pin input enabled
Falling waveform/“L” level (“L” level is recognized with
Interrupt valid waveform for INT1 0
the SNZI1 instruction)
I22 pin/return level selection bit
Rising waveform/“H” level (“H” level is recognized with
(Note 2)
1
the SNZI1 instruction)
INT1 pin edge detection circuit 0 One-sided edge detected
I21
control bit
1 Both edges detected
INT1 pin Timer 3 count start 0 Timer 3 count start synchronous circuit not selected
I20
synchronous circuit selection bit 1 Timer 3 count start synchronous circuit selected
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I22 and I23 are changed, the external interrupt request flag EXF1 may be
set. Accordingly, clear EXF1 flag with the SNZ1 instruction when the bit 1 (V11) of register V1 to
“0”. In this time, set the NOP instruction after the SNZ1 instruction, for the case when a skip is
performed with the SNZ1 instruction.
3: When setting the power down, I21–I20 are not used.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-81