4524_M Datasheet, PDF (195/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.2 Interrupts
➀ Disable Interrupts
Timer 5 interrupt is temporarily disabled.
Interrupt enable flag INTE
Interrupt control register V2
0
b3
b0
✕✕ 0 ✕
All interrupts disabled [DI]
b1: Timer 5 interrupt occurrence disabled [TV2A]
➁ Set Timer Value
Timer 5 is temporarily stopped.
Timer 5 count time is set.
(The formula is shown *A below.)
Timer control register W5
↓
b3
b0
✕0 0 1
[TW5A]
b2: Timer 5 stop
Timer 5 count value initialized
b1,b0: Timer count value 2¹⁴ set
↓
➂ Clear Interrupt Request
Timer 5 interrupt activated condition is cleared.
Timer 5 interrupt request flag T5F 0
Timer 5 interrupt activated condition cleared [SNZT5]
↓
( ) Note when the interrupt request is cleared
When ➂ is executed, considering the skip of the next instruction
according to the interrupt request flag T5F,
insert the NOP instruction after the SNZT5 instruction.
➃ Start Timer Operation
Timer 5 temporarily stopped is restarted.
Timer control register W5
↓
b3
b0
✕1 0 1
b2: Timer 5 operation start [TW5A]
↓
➄ Enable Interrupts
The Timer 5 interrupt which is temporarily disabled is enabled.
Interrupt control register V2
b3
b0
✕ ✕ 1 ✕ b1: Timer 5 interrupt occurrence enabled [TV2A]
Interrupt enable flag INTE 1
All interrupts enabled [EI]
↓
Constant period interrupt execution started
*A: The timer 5 count value to make the interrupt occur every 500 ms is set as follows.
500 ms = (32.768 kHz)^–1 ✕ 2¹⁴
Sub-clock
Timer 5 count value
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Fig. 2.2.9 Timer 5 constant period interrupt setting example
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
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