4524_M Datasheet, PDF (230/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.6 LCD function
2.6 LCD function
The 4524 Group has an LCD (Liquid Crystal Display) controller/driver.
4 common signal output pins and 20 segment signal output pins can be used to drive the LCD. By using
these pins, up to 80 segments (when 1/4 duty and 1/3 bias are selected) can be controlled to display.
This section describes the LCD operation description, related registers, application examples using the LCD
and notes.
2.6.1 Operation description
(1) LCD duty and bias control
Table 2.6.1 shows the duty and maximum number of displayed pixels. Use bits 0 and 1 of LCD
control register (L1) to select the proper display method for the LCD panel being used.
The LCD power input pins (VLC1–VLC3) are also used as pins SEG0–SEG2. The internal power (VDD)
is used for the LCD power.
Table 2.6.1 Duty and maximum number of
displayed pixels
Maximum number
Duty Bias
of displayed pixels
Used COM pins
1/2 1/2 40 segments COM0, COM1 (Note)
1/3 1/3 60 segments COM0–COM2 (Note)
1/4 1/3 80 segments
COM0–COM3
Note: Leave unused COM pins open.
T54
ORCLK
W62
0
1
➀
(Note)
W63
➁
0
➂
Timer LC (4)
1
1/2
Reload register RLC (4)
(TLCA) _(TLCA)
Register A
Note: Count source is stopped by setting “0” to this bit.
LCD
clock
Fig. 2.6.1 LCD clock control circuit structure
(2) LCD drive timing
The LCD clock frequency (F) and frame frequency generating the LCD drive timing are shown below.
Figure 2.6.1 shows the structure of the LCD clock circuit.
q When the prescaler output (ORCLK) is used for the timer LC count source (W62 = “1”)
F = ORCLK ✕ ¹ ✕ ¹
LC + 1 2
➀
➁
➂
q When bit 4 (T54) of timer 5 is used for the timer LC count source (W62 = “0”)
F = T54 ✕
1 _✕1
LC + 1 2
➀
➁
➂
The frame frequency for each display method can be obtained by the following formula.
Frame frequency = ^F (Hz)
n
[F: Frame frequency, 1/n: Duty]
Frame period = ⁿ (s)
F
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-66