4524_M Datasheet, PDF (199/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.3 Timers
(3) Interrupt control register I3
Table 2.3.3 shows the interrupt control register I3.
Set the contents of this register through register A with the TI3A instruction.
In addition, the TAI3 instruction can be used to transfer the contents of register I3 to register A.
Table 2.3.3 Interrupt control register I3
Interrupt control register I3
at reset : 02
at power down : state retained R/W
Timer 4, serial I/O interrupt 0 Timer 4 interrupt valid, serial I/O interrupt invalid
I30
source selection bit
1 Serial I/O interrupt valid, timer 4 interrupt invalid
Note: “R” represents read enabled, and “W” represents write enabled.
(4) Timer control register PA
Table 2.3.4 shows the timer control register PA.
Set the contents of this register through register A with the TPAA instruction.
Table 2.3.4 Timer control register PA
Timer control register PA
at reset : 02
at power down : state retained
W
PA0 Prescaler control bit
Note: “W” represents write enabled.
0 Stop (state initialized)
1 Operating
(5) Timer control register W1
Table 2.3.5 shows the timer control register W1.
Set the contents of this register through register A with the TW1A instruction.
In addition, the TAW1 instruction can be used to transfer the contents of register W1 to register A.
Table 2.3.5 Timer control register W1
Timer control register W1
at reset : 00002 at power down : state retained R/W
W13 ^{Timer 1 count auto-stop circuit}
control bit (Note 2)
0 Timer 1 count auto-stop circuit not selected
1 Timer 1 count auto-stop circuit selected
W12 _{Timer 1 control bit}
0 Stop (state retained)
1 Operating
W11
W10
W11 W10
Count source
0
Timer 1 count source selection ₀
bits
1
0 Instruction clock (INSTCK)
1 Prescaler output (ORCLK)
0 Timer 5 underflow signal (T5UDF)
1 1 CNTR0 input
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”).
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-35