4524_M Datasheet, PDF (217/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.4 A/D converter
➀ Disable Interrupts
A/D interrupt is temporarily disabled.
Interrupt enable flag INTE
Interrupt control register V2
0
b3
b0
✕0 ✕✕
All interrupts disabled [DI]
b2: A/D interrupt occurrence disabled [TV2A]
↓
➁ Set A/D Converter
A/D conversion mode is selected to A/D operation mode.
Analog input pin AIN0 is selected.
A/D control register Q2
b3
b0
✕✕✕ 1
b3
b0
A/D control register Q1 0 0 0 0
b0: AIN0 pin function selected [TQ2A]
A/D conversion selected, AIN0 selected [TQ1A]
➂ Clear Interrupt Request
A/D interrupt activated condition is cleared.
A/D conversion completion flag ADF 0
↓
A/D interrupt activated condition cleared [SNZAD]
↓
( ) Note when the interrupt request is cleared
When ➂ is executed, considering the skip of the next instruction
according to the flag ADF, insert the NOP instruction after the SNZAD instruction.
↓
↓
When interrupt is not used
➃ Set Interrupt
Interrupts except A/D conversion is enabled. [EI]
↓
When interrupt is used
➃ Set Interrupt
A/D interrupt temporarily disabled is enabled.
b3
b0
Interrupt control register V2 ✕ 1 ✕ ✕
b2: A/D interrupt occurrence enabled [TV2A]
Interrupt enable flag INTE 1
All interrupt enabled [EI]
↓
↓
↓
➄ Start A/D Conversion
A/D conversion operation is started [ADST]
↓
↓
↓
When interrupt is not used
➅ Check A/D Interrupt Request
A/D conversion completion flag is checked [SNZAD]
When interrupt is used
➅ A/D Interrupt Occur
↓
➆ Execute A/D Conversion
High-order 8 bits of register AD
Low-order 2 bits of register AD
↓
↓
→
Register A and register B [TABAD]
→
High-order 2 bits of register A [TALA]
“0” is set to low-order 2 bits of register A
↓
When A/D conversion is executed by the same channel, repeat ➄ to ➆.
When A/D conversion is executed by another channel, repeat ➀ to ➆.
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Fig. 2.4.2 A/D conversion mode setting example
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
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