4524_M Datasheet, PDF (184/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.2 Interrupts
(4) Interrupt control register V2
Table 2.2.2 shows the interrupt control register V2.
Set the contents of this register through register A with the TV2A instruction.
In addition, the TAV2 instruction can be used to transfer the contents of register V2 to register A.
Table 2.2.2 Interrupt control register V2
Interrupt control register V2
at reset : 00002
at power down : 00002
R/W
Timer 4, serial I/O interrupt 0 Interrupt disabled (SNZT4, SNZSI instruction is valid)
V23
enable bit (Note 2)
1 Interrupt enabled (SNZT4, SNZSI instruction is invalid) (Note 3)
V22 A/D interrupt enable bit
0 Interrupt disabled (SNZAD instruction is valid)
1 Interrupt enabled (SNZAD instruction is invalid) (Note 3)
V21 Timer 5 interrupt enable bit
0 Interrupt disabled (SNZT5 instruction is valid)
1 Interrupt enabled (SNZT5 instruction is invalid) (Note 3)
V20 Timer 3 interrupt enable bit
0 Interrupt disabled (SNZT3 instruction is valid)
1 Interrupt enabled (SNZT3 instruction is invalid) (Note 3)
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Select the timer 4 interrupt or serial I/O interrupt by the timer 4, serial I/O interrupt source
selection bit (I30).
3: These instructions are equivalent to the NOP instruction.
(5) Interrupt control register I1
Table 2.2.3 shows the interrupt control register I1.
Set the contents of this register through register A with the TI1A instruction.
In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A.
Table 2.2.3 Interrupt control register I1
Interrupt control register I1
at reset : 00002 at power down : state retained R/W
0 INT0 pin input disabled
I13 INT0 pin input control bit (Note 2)
1 INT0 pin input enabled
Falling waveform /“L” level (“L” level is recognized with
Interrupt valid waveform for INT0 0
the SNZI0 instruction)
I12 pin/return level selection bit
Rising waveform /“H” level (“H” level is recognized with
(Note 2)
1
the SNZI0 instruction)
INT0 pin edge detection circuit 0 One-sided edge detected
I11
control bit
1 Both edges detected
INT0 pin Timer 1 count start 0 Timer 1 count start synchronous circuit not selected
I10
synchronous circuit selection bit 1 Timer 1 count start synchronous circuit selected
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be
set. Accordingly, clear EXF0 flag with the SNZ0 instruction when the bit 0 (V10) of register V1 to
“0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is
performed with the SNZ0 instruction.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-20