4524_M Datasheet, PDF (12/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
List of tables
List of tables
CHAPTER 1 HARDWARE
Table Selection of system clock ..................................................................................................... 7
Table 1 ROM size and pages ....................................................................................................... 21
Table 2 RAM size ........................................................................................................................... 22
Table 3 Interrupt sources ............................................................................................................... 23
Table 4 Interrupt request flag, interrupt enable bit and skip instruction ................................. 23
Table 5 Interrupt enable bit function ............................................................................................ 23
Table 6 Interrupt control registers ................................................................................................ 25
Table 7 External interrupt activated conditions ........................................................................... 27
Table 8 External interrupt control register ................................................................................... 29
Table 9 Function related timers .................................................................................................... 33
Table 10 Timer related registers ................................................................................................... 36
Table 11 A/D converter characteristics ........................................................................................ 47
Table 12 A/D control registers ...................................................................................................... 48
Table 13 Change of successive comparison register AD during A/D conversion ................. 49
Table 14 Serial I/O pins ................................................................................................................. 53
Table 15 Serial I/O control register .............................................................................................. 53
Table 16 Processing sequence of data transfer from master to slave ................................... 56
Table 17 Duty and maximum number of displayed pixels ........................................................ 57
Table 18 LCD control registers ..................................................................................................... 59
Table 19 Port state at reset .......................................................................................................... 63
Table 20 Voltage drop detection circuit operation state ............................................................ 66
Table 21 Functions and states retained at power down ........................................................... 67
Table 22 Return source and return condition ............................................................................. 68
Table 23 Key-on wakeup control register, pull-up control register and interrupt control register ...... 70
Table 24 Clock control register MR ............................................................................................. 74
Table 25 Product of built-in PROM version .............................................................................. 150
CHAPTER 2 APPLICATION
Table 2.1.1 Timer control register W3 ........................................................................................... 5
Table 2.1.2 Timer control register W4 ........................................................................................... 5
Table 2.1.3 Timer control register W6 ........................................................................................... 6
Table 2.1.4 Serial I/O control register J1 ...................................................................................... 6
Table 2.1.5 A/D control register Q2 ............................................................................................... 7
Table 2.1.6 A/D control register Q3 ............................................................................................... 7
Table 2.1.7 Pull-up control register PU0 ....................................................................................... 8
Table 2.1.8 Pull-up control register PU1 ....................................................................................... 8
Table 2.1.9 Port output structure control register FR0 ................................................................ 9
Table 2.1.10 Port output structure control register FR1 .............................................................. 9
Table 2.1.11 Port output structure control register FR2 ............................................................ 10
Table 2.1.12 Port output structure control register FR3 ............................................................ 10
Table 2.1.13 Key-on wakeup control register K0 ....................................................................... 11
Table 2.1.14 Key-on wakeup control register K1 ....................................................................... 11
Table 2.1.15 Key-on wakeup control register K2 ....................................................................... 12
Table 2.1.16 Connections of unused pins ................................................................................... 15
Rev.2.00 Aug, 06 2004
viii
REJ09B0107-0200Z