4524_M Datasheet, PDF (182/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.2 Interrupts
(7) A/D interrupt
The interrupt request occurs by the completion of A/D conversion.
s A/D interrupt processing
q When the interrupt is used
The interrupt occurrence is enabled when the bit 2 of the interrupt control register V2 and the
interrupt enable flag INTE are set to “1.” When the A/D interrupt occurs, the interrupt processing
is executed from address C in page 1.
q When the interrupt is not used
The interrupt is disabled and the SNZAD instruction is valid when the bit 2 of register V2 is set
to “0.”
(8) Timer 4 interrupt
The interrupt request occurs by the timer 4 underflow.
s Timer 4 interrupt processing
q When the interrupt is used
The interrupt occurrence is enabled when the bit 3 of the interrupt control register V2 and the
interrupt enable flag INTE are set to “1.” When the timer 4 interrupt occurs, the interrupt processing
is executed from address E in page 1.
q When the interrupt is not used
The interrupt is disabled and the SNZT4 instruction is valid when the bit 3 of register V2 is set
to “0.”
(9) Serial I/O interrupt
The interrupt request occurs by the completion of serial I/O transmit/receive.
However, set the timer 4, serial I/O interrupt source selection bit (I30) to “1.”
s Serial I/O interrupt processing
q When the interrupt is used
The interrupt occurrence is enabled when the bit 3 of the interrupt control register V2 and the
interrupt enable flag INTE are set to “1.” When the serial I/O interrupt occurs, the interrupt
processing is executed from address E in page 1.
q When the interrupt is not used
The interrupt is disabled and the SNZSI instruction is valid when the bit 3 of register V2 is set
to “0.”
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-18