4524_M Datasheet, PDF(185/310 Page) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

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4524_M Datasheet, PDF (185/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

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4524 Group

APPLICATION

2.2 Interrupts

(6) Interrupt control register I2

Table 2.2.4 shows the interrupt control register I2.

Set the contents of this register through register A with the TI2A instruction.

In addition, the TAI2 instruction can be used to transfer the contents of register I2 to register A.

Table 2.2.4 Interrupt control register I2

Interrupt control register I2

at reset : 00002 at power down : state retained R/W

0 INT1 pin input disabled

I23 INT1 pin input control bit (Note 2)

1 INT1 pin input enabled

Falling waveform /âLâ level (âLâ level is recognized with

Interrupt valid waveform for INT1 0

the SNZI1 instruction)

I22 pin/return level selection bit

Rising waveform /âHâ level (âHâ level is recognized with

(Note 2)

1

the SNZI1 instruction)

INT1 pin edge detection circuit 0 One-sided edge detected

I21

control bit

1 Both edges detected

INT1 pin Timer 3 count start 0 Timer 3 count start synchronous circuit not selected

I20

synchronous circuit selection bit 1 Timer 3 count start synchronous circuit selected

Notes 1: âRâ represents read enabled, and âWâ represents write enabled.

2: When the contents of I22 and I23 are changed, the external interrupt request flag EXF1 may be

set. Accordingly, clear EXF1 flag with the SNZ1 instruction when the bit 1 (V11) of register V1 to

â0â. In this time, set the NOP instruction after the SNZ1 instruction, for the case when a skip is

performed with the SNZ1 instruction.

(7) Interrupt control register I3

Table 2.2.5 shows the interrupt control register I3.

Set the contents of this register through register A with the TI3A instruction.

In addition, the TAI3 instruction can be used to transfer the contents of register I3 to register A.

Table 2.2.5 Interrupt control register I3

Interrupt control register I3

at reset : 02

at power down : state retained R/W

Timer 4, serial I/O interrupt 0 Timer 4 interrupt valid, serial I/O interrupt invalid

I30

source selection bit

1 Serial I/O interrupt valid, timer 4 interrupt invalid

Note: âRâ represents read enabled, and âWâ represents write enabled.

Rev.2.00 Aug, 06 2004

REJ09B0107-0200Z

2-21

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