4524_M Datasheet, PDF (201/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.3 Timers
(8) Timer control register W4
Table 2.3.8 shows the timer control register W4.
Set the contents of this register through register A with the TW4A instruction.
In addition, the TAW4 instruction can be used to transfer the contents of register W4 to register A.
Table 2.3.8 Timer control register W4
Timer control register W4
at reset : 00002
at power down : 00002
R/W
W43 CNTR1 output control bit
0 CNTR1 output invalid
1 CNTR1 output valid
P W M s i g n a l “ H ” i n t e r v a l 0 PWM signal “H” interval expansion function invalid
W42
expansion function control bit
1 PWM signal “H” interval expansion function valid
W41 Timer 4 control bit
0 Stop (state retained)
1 Operating
Timer 4 count source selection 0 XIN input
W40
bit
1 Prescaler output (ORCLK) divided by 2
Note: “R” represents read enabled, and “W” represents write enabled.
(9) Timer control register W5
Table 2.3.9 shows the timer control register W5.
Set the contents of this register through register A with the TW5A instruction.
In addition, the TAW5 instruction can be used to transfer the contents of register W5 to register A.
Table 2.3.9 Timer control register W5
Timer control register W5
at reset : 00002 at power down : state retained R/W
W53
W52
W51
Not used
0
This bit has no function, but read/write is enabled.
1
Timer 5 control bit
0 Stop (state initialized)
1 Operating
W51 W50
Count value
Timer 5 count value selection bits ^{0 0 Underflow occurs every 8192 counts}
0 1 Underflow occurs every 16384 counts
W50
1 0 Underflow occurs every 32768 counts
1 1 Underflow occurs every 65536 counts
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When timer is used, W53 is not used.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-37