4524_M Datasheet, PDF (221/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.5 Serial I/O
2.5.2 Related registers
(1) Serial I/O register SI
Serial I/O register SI is the 8-bit data transfer serial/parallel conversion register. Data can be set to
register SI through registers A and B with the TSIAB instruction.
Also, the low-order 4 bits of register SI is transferred to register A, and the high-order 4 bits of
register SI is transferred to register B with the TABSI instruction.
(2) Serial I/O transmit/receive completion flag (SIOF)
Serial I/O transmit/receive completion flag (SIOF) is set to “1” when serial data transmit or receive
operation completes. The state of SIOF flag can be examined with the skip instruction (SNZSI).
(3) Interrupt control register V2
Table 2.5.1 shows the interrupt control register V2.
Set the contents of this register through register A with the TV2A instruction.
In addition, the TAV2 instruction can be used to transfer the contents of register V2 to register A.
Table 2.5.1 Interrupt control register V2
Interrupt control register V2
at reset : 00002
at power down : 00002
R/W
Timer 4, serial I/O interrupt 0 Interrupt disabled (SNZT4, SNZSI instruction is valid)
V23
enable bit (Note 2)
1 Interrupt enabled (SNZT4, SNZSI instruction is invalid) (Note 3)
V22 A/D interrupt enable bit
0 Interrupt disabled (SNZAD instruction is valid)
1 Interrupt enabled (SNZAD instruction is invalid) (Note 3)
V21 Timer 5 interrupt enable bit
0 Interrupt disabled (SNZT5 instruction is valid)
1 Interrupt enabled (SNZT5 instruction is invalid) (Note 3)
V20 Timer 3 interrupt enable bit
0 Interrupt disabled (SNZT3 instruction is valid)
1 Interrupt enabled (SNZT3 instruction is invalid) (Note 3)
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Select the timer 4 interrupt or serial I/O interrupt by the timer 4, serial I/O interrupt source
selection bit (I30).
3: These instructions are equivalent to the NOP instruction.
4: When setting the Serial I/O, V23, V21 and V20 are not used.
(4) Interrupt control register I3
Table 2.5.2 shows the interrupt control register I3.
Set the contents of this register through register A with the TI3A instruction.
In addition, the TAI3 instruction can be used to transfer the contents of register I3 to register A.
Table 2.5.2 Interrupt control register I3
Interrupt control register I3
at reset : 02
at power down : state retained R/W
Timer 4, serial I/O interrupt 0 Timer 4 interrupt valid, serial I/O interrupt invalid
I30
source selection bit
1 Serial I/O interrupt valid, timer 4 interrupt invalid
Note: “R” represents read enabled, and “W” represents write enabled.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-57