4524_M Datasheet, PDF (9/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
List of figures
Fig. 38 Serial I/O structure ............................................................................................................ 53
Fig. 39 Serial I/O register state when transfer ........................................................................... 54
Fig. 40 Serial I/O connection example ......................................................................................... 55
Fig. 41 Timing of serial I/O data transfer .................................................................................... 55
Fig. 42 LCD clock control circuit structure .................................................................................. 57
Fig. 43 LCD controller/driver ......................................................................................................... 58
Fig. 44 LCD RAM map ................................................................................................................... 59
Fig. 45 LCD controller/driver structure ......................................................................................... 60
Fig. 46 LCD power source circuit example (1/3 bias condition selected) .............................. 61
Fig. 47 Reset release timing ......................................................................................................... 62
Fig. 48 RESET pin input waveform and reset operation .......................................................... 62
Fig. 49 Structure of reset pin and its peripherals, and power-on reset operation ................ 63
Fig. 50 Internal state at reset ....................................................................................................... 64
Fig. 51 Internal state at reset ....................................................................................................... 65
Fig. 52 Voltage drop detection reset circuit ................................................................................ 66
Fig. 53 Voltage drop detection circuit operation waveform ....................................................... 66
Fig. 54 V and V 66 DD
RST ...............................................................................................................................................................................................................
Fig. 55 State transition ................................................................................................................... 69
Fig. 56 Set source and clear source of the P flag .................................................................... 69
Fig. 57 Start condition identified example using the SNZP instruction ................................... 69
Fig. 58 Clock control circuit structure .......................................................................................... 72
Fig. 59 Switch to ceramic oscillation/RC oscillation ................................................................... 73
Fig. 60 Handling of XIN and XOUT when operating on-chip oscillator ....................................... 73
Fig. 61 Ceramic resonator external circuit .................................................................................. 73
Fig. 62 External RC oscillation circuit .......................................................................................... 73
Fig. 63 External clock input circuit ............................................................................................... 74
Fig. 64 External quartz-crystal circuit ........................................................................................... 74
Fig. 65 External 0 interrupt program example-1 ......................................................................... 76
Fig. 66 External 0 interrupt program example-2 ......................................................................... 76
Fig. 67 External 0 interrupt program example-3 ......................................................................... 76
Fig. 69 External 1 interrupt program example-2 ......................................................................... 77
Fig. 70 External 1 interrupt program example-3 ......................................................................... 77
Fig. 71 A/D converter program example-3 .................................................................................. 77
Fig. 72 Analog input external circuit example-1 ......................................................................... 78
Fig. 73 Analog input external circuit example-2 ......................................................................... 78
Fig. 74 V and V 78 DD
RST ...............................................................................................................................................................................................................
Fig. 75 Pin configuration of built-in PROM version ................................................................. 150
Fig. 76 PROM memory map ........................................................................................................ 151
Fig. 77 Flow of writing and test of the product shipped in blank .......................................... 151
CHAPTER 2 APPLICATION
Fig. 2.1.1 Key input by key scan .................................................................................................. 13
Fig. 2.1.2 Key scan input timing ................................................................................................... 13
Fig. 2.2.1 External 0 interrupt operation example ...................................................................... 23
Fig. 2.2.2 External 0 interrupt setting example .......................................................................... 24
Fig. 2.2.3 External 1 interrupt operation example ...................................................................... 25
Fig. 2.2.4 External 1 interrupt setting example .......................................................................... 26
Fig. 2.2.5 Timer 1 constant period interrupt setting example ................................................... 27
Fig. 2.2.6 Timer 2 constant period interrupt setting example ................................................... 28
Fig. 2.2.7 Timer 3 constant period interrupt setting example ................................................... 29
Fig. 2.2.8 Timer 4 constant period interrupt setting example ................................................... 30
Fig. 2.2.9 Timer 5 constant period interrupt setting example ................................................... 31
Rev.2.00 Aug, 06 2004
v
REJ09B0107-0200Z