4524_M Datasheet, PDF (300/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPENDIX
3.3 List of precautions
3.3.11 Notes on power down
(1) POF instruction, POF2 instruction
Execute the POF or POF2 instruction immediately after executing the EPOF instruction to enter the
power down state.
Note that system cannot enter the power down state when executing only the POF or POF2 instruction.
Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction
and the POF or POF2 instruction.
(2) Key-on wakeup function
After checking none of the return condition for ports (P0, P1, INT0 and INT1 specified with register
K0–K2) with valid key-on wakeup function is satisfied, execute the POF or POF2 instruction.
If at least one of return condition for ports with valid key-on wakeup function is satisfied, system
returns from the power downn state immediately after the POF or POF2 instruction is executed.
(3) Timer 5 interrupt request flag
When POF or POF2 instruction is executed while T5F is “1”, system returns from the power down
state immediately.
(4) Return from power down mode
After system returns from power down mode, set the undefined registers and flags.
The initial value of the following registers are undefined at power down. After system is returned from
power down mode, set initial values.
• Register Z (2 bits)
• Register X (4 bits)
• Register Y (4 bits)
• Register D (3 bits)
• Register E (8 bits)
(5) Watchdog timer
• The watchdog timer function is valid after system is returned from the power down state. When not
using the watchdog timer function, stop the watchdog timer function with the DWDT instruction and
the WRST instruction continuously every system is returned from the power down.
• When the watchdog timer function and power down function are used at the same time, initialize
the flag WDF1 with the WRST instruction before system goes into the power down state.
(6) Port D8/INT0 pin
When the power down mode is used by clearing the bit 3 of register I1 to “0” and setting the input
of INT0 pin to be disabled, be careful about the following note.
• When the input of INT0 pin is disabled (register I13 = “0”), clear bit 0 of register K2 to “0” to
invalidate the key-on wakeup before system goes into the power down mode.
(7) Port D9/INT1 pin
When the power down mode is used by clearing the bit 3 of register I2 to “0” and setting the input
of INT1 pin to be disabled, be careful about the following note.
• When the input of INT1 pin is disabled (register I23 = “0”), clear bit 2 of register K2 to “0” to
invalidate the key-on wakeup before system goes into the power down mode.
(8) External clock
When the external clock signal is used as the main clock (f(XIN)), note that the power down mode
(POF or POF2 instruction) cannot be used.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
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