4524_M Datasheet, PDF (223/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.5 Serial I/O
2.5.3 Operation description
Figure 2.5.2 shows the serial I/O connection example, Figure 2.5.3 shows the serial I/O register state, and
Figure 2.5.4 shows the serial I/O transfer timing.
Master (internal clock selected)
4524
Slave (external clock selected)
4524
Control signal
D3
D3
SCK
SCK
SOUT
SIN
SIN
SOUT
Note: The control signal is used to inform the master by the pin level
that the slave is in a ready state to receive.
The 4524 Group does not have a control pin exclusively
used for serial I/O.
Accordingly, if a control signal is required, use the normal input/output ports.
Fig. 2.5.2 Serial I/O connection example
Master (M7–M0 : transfer data)
SIN pin
Serial I/O register (SI)
SOUT pin
M7 M6 M5 M4 M3 M2 M1 M0
Slave (S7–S0: transfer data)
SOUT pin
SIN pin
Serial I/O register (SI)
S7 S6 S5 S4 S3 S2 S1 S0
* ^{M7 M6 M5 M4 M3 M2 M1}
S0 M7 M6 M5 M4 M3 M2 M1
* ^{S0 M7 M6 M5 M4 M3 M2}
S7 S6 S5 S4 S3 S2 S1 S0
Transfer data set
Transfer start
Falling of clock
S7 S6 S5 S4 S3 S2 S1 S0
* ^{S7 S6 S5 S4 S3 S2 S1}
Rising of clock
M0 S7 S6 S5 S4 S3 S2 S1
Falling of clock
* ^{M0 S7 S6 S5 S4 S3 S2}
Transfer complete _{M7 M6 M5 M4 M3 M2 M1 M0}
Fig. 2.5.3 Serial I/O register state when transfer
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-59