4524_M Datasheet, PDF (253/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.10 Oscillation circuit
2.10.2 Oscillation operation
System clock is supplied to CPU and peripheral device as the base clock for the microcomputer operation.
For the 4524 Group, the clock supplied is selected from the following;
q on-chip oscillator (internal oscillator),
q the ceramic oscillation circuit, and
q divided clock supplied from RC oscillation circuit. Its division ratio is selected from the following with the
register MR;
• through mode (f(XIN)) (not divided),
• frequency divided by 2 mode (f(XIN)/2),
• frequency divided by 4 mode (f(XIN)/4) or
• frequency divided by 8 mode (f(XIN)/8).
Figure 2.10.7 shows the structure of the clock control circuit.
On-chip oscillator
(internal oscillator)
(Note 1)
RC oscillation
circuit
XIN
XOUT
Ceramic
oscillation circuit
XCIN
XCOUT
Quartz-crystal
oscillation circuit
Multi-plexer
MR0
0
1
QS
QR
Division circuit
Divided by 8
Divided by 4
Divided by 2
MR3, MR2
11
10
01
00
System clock (STCK)
Internal clock
generating circuit
(divided by 3)
Instruction clock
(INSTCK)
Wait time
control circuit
(Note 2)
Program start
signal
QS
R
CRCK instruction
QS
R
MR1
QS
R
EPOF instruction +
CMCK instruction
Internal reset signal
T5F flag
Key-on wakeup signal
POF instruction
QS
R
EPOF instruction + POF2 instruction
Notes 1: System operates by the on-chip oscillator clock (f(RING)) until the CMCK or CRCK instruction is executed
after system is released from reset.
2: The wait time control circuit is used to generate the time required to stabilize the f(XIN) or f(XCIN) oscillation.
After the certain oscillation stabilizing wait time elapses, the program start signal is output.
This circuit operates when system is released from reset or returned from power down.
Fig. 2.10.7 Structure of clock control circuit
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-89