4524_M Datasheet, PDF (237/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.7 Reset
2.7.2 Internal state at reset
Figure 2.7.3 shows the internal state at reset. The contents of timers, registers, flags and RAM other than
shown in Figure 2.7.3 are undefined, so that set them to initial values.
• Program counter (PC) .....................................................0.....0......0.....0.....0.....0.. 0 0 0 0 0 0 0 0
Address 0 in page 0 is set to program counter.
• Interrupt enable flag (INTE) .....................................................................0.. (Interrupt disabled)
• Power down flag (P) .................................................................................0..
• External 0 interrupt request flag (EXF0) ................................................0..
• External 1 interrupt request flag (EXF1) ................................................0..
• Interrupt control register V1 ......................................................0.....0.....0.....0.. (Interrupt disabled)
• Interrupt control register V2 ......................................................0.....0.....0.....0.. (Interrupt disabled)
• Interrupt control register I1 ........................................................0.....0.....0.....0..
• Interrupt control register I2 ........................................................0.....0.....0.....0..
• Interrupt control register I3 .......................................................................0..
• Timer 1 interrupt request flag (T1F) .......................................................0..
• Timer 2 interrupt request flag (T2F) .......................................................0..
• Timer 3 interrupt request flag (T3F) .......................................................0..
• Timer 4 interrupt request flag (T4F) .......................................................0..
• Timer 5 interrupt request flag (T5F) .......................................................0..
• Watchdog timer flags (WDF1, WDF2) ....................................................0..
• Watchdog timer enable flag (WEF) .........................................................1..
• Timer control register PA .........................................................................0.. (Prescaler stopped)
• Timer control register W1 ..........................................................0.....0.....0.....0.. (Timer 1 stopped)
• Timer control register W2 ..........................................................0.....0.....0.....0.. (Timer 2 stopped)
• Timer control register W3 ..........................................................0.....0.....0.....0.. (Timer 3 stopped)
• Timer control register W4 ..........................................................0.....0.....0.....0.. (Timer 4 stopped)
• Timer control register W5 ..........................................................0.....0.....0.....0.. (Timer 5 stopped)
• Timer control register W6 ..........................................................0.....0.....0.....0.. (Timer LC stopped)
• Clock control register MR ..........................................................1.....1.....0.....0..
• Serial I/O transmit/receive completion flag (SIOF) ...............................0..
• Serial I/O mode register J1 .......................................................0.....0.....0.....0.. (External clock selected,
serial I/O port not selected)
• Serial I/O register SI .............................................✕.....✕.....✕.....✕.....✕.....✕.....✕.....✕...
• A/D conversion completion flag (ADF) ...................................................0..
• A/D control register Q1 ..............................................................0.....0.....0.....0..
• A/D control register Q2 ..............................................................0.....0.....0.....0..
• A/D control register Q3 ..............................................................0.....0.....0.....0..
• Successive approximation register AD .....✕.....✕.....✕.....✕.....✕.....✕.....✕.....✕.....✕.....✕...
• Comparator register ...............................................✕.....✕.....✕.....✕.....✕.....✕.....✕.....✕...
• LCD control register L1 .............................................................0.....0.....0.....0..
• LCD control register L2 .............................................................1.....1.....1.....1..
Fig. 2.7.3 Internal state at reset
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
“✕” represents undefined.
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