4524_M Datasheet, PDF (298/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPENDIX
3.3 List of precautions
(5) A/D converter is used at the comparator mode
The analog input voltage is higher than the comparison voltage as a result of comparison, the
contents of ADF flag retains “0,” not set to “1.”
In this case, the A/D interrupt does not occur even when the usage of the A/D interrupt is enabled.
Accordingly, consider the time until the comparator operation is completed, and examine the state
of ADF flag by software. The comparator operation is completed after 8 machine cycles.
(6) Analog input pins
When P20/AIN0–P23/AIN3, P30/AIN4–P33/AIN7 are set to pins for analog input, they cannot be used as
I/O ports P2 and P3.
(7) TALA instruction
When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-
order 2 bits of register A, and simultaneously, the low-order 2 bits of register A is “0.”
(8) Recommended operating conditions when using A/D converter
The recommended operating conditions of supply voltage and system clock frequency when using A/
D converter are different from those when not using A/D converter.
Table 3.3.2 shows the recommended operating conditions when using A/D converter.
Table 3.3.2 Recommended operating conditions (when using A/D converter)
Parameter
Condition
Limits
Unit
Min. Typ. Max.
System clock frequency VDD = 4.0 to 5.5 V (through mode)
0.1
6.0 MHz
(at ceramic resonance) VDD = 2.7 to 5.5 V (through mode)
0.1
4.4
(Note 2)
VDD = 2.7 to 5.5 V (Frequency/2 mode)
0.1
3.0
VDD = 2.7 to 5.5 V (Frequency/4 mode)
0.1
1.5
VDD = 2.7 to 5.5 V (Frequency/8 mode)
0.1
0.7
System clock frequency VDD = 2.7 to 5.5 V (through mode)
0.1
4.4 MHz
(at RC oscillation)
VDD = 2.7 to 5.5 V (Frequency/2 mode)
0.1
2.2
(Note 2)
VDD = 2.7 to 5.5 V (Frequency/4 mode)
0.1
1.1
VDD = 2.7 to 5.5 V (Frequency/8 mode)
0.1
0.5
System clock frequency VDD = 4.0 to 5.5 V (through mode)
0.1
4.8 MHz
(ceramic resonance
VDD = 2.7 to 5.5 V (through mode)
0.1
3.2
selected, at external VDD = 2.7 to 5.5 V (Frequency/2 mode)
0.1
2.4
clock input)
VDD = 2.7 to 5.5 V (Frequency/4 mode)
0.1
1.2
VDD = 2.7 to 5.5 V (Frequency/8 mode)
0.1
0.6
Note: The frequency at RC oscillation is affected by a capacitor, a resistor and a microcomputer. So, set
the constants within the range of the frequency limits.
3.3.7 Notes on serial I/O
(1) Note when an external clock is used as a synchronous clock:
• An external clock is selected as the synchronous clock, the clock is not controlled internally.
• Serial transmit/receive is continued as long as an external clock is input. If an external clock is input
9 times or more and serial transmit/receive is continued, the receive data is transferred directly as
transmit data, so that be sure to control the clock externally.
Note also that the SIOF flag is set to “1” when a clock is counted 8 times.
• Be sure to set the initial input level on the external clock pin to “H” level.
• Refer to section “3.1 Electrical characteristics” when using serial I/O with an external clock.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
3-44