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| 4524_M Datasheet, PDF (159/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES | |||
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4524 Group
HARDWARE
INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Parameter
Instruction code
Mnemonic
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecimal
notation
TABAD
1 0 0 1 1 1 1 0 0 1 279 1
TALA
1 0 0 1 0 0 1 0 0 1 249 1
TADAB
1 0 0 0 1 1 1 0 0 1 239 1
Function
1 Q13 = 0:
(B) â (AD9âAD6)
(A) â (AD5âAD2)
Q13 = 1:
(B) â (AD7âAD4)
(A) â (AD3âAD0)
1 (A3, A2) â (AD1, AD0)
(A1, A0) â 0
1 (AD7âAD4) â (B)
(AD3âAD0) â (A)
ADST
1010011111
29F 1
1 (ADF) â 0
A/D conversion starting
SNZAD
1010000111
2 8 7 1 1 V22 = 0: (ADF) = 1 ?
After skipping, (ADF) â 0 V22 = 1: NOP
TAQ1
TQ1A
TAQ2
TQ2A
TAQ3
TQ3A
NOP
POF
1 0 0 1 0 0 0 1 0 0 2 4 4 1 1 (A) â (Q1)
1 0 0 0 0 0 0 1 0 0 2 0 4 1 1 (Q1) â (A)
1 0 0 1 0 0 0 1 0 1 2 4 5 1 1 (A) â (Q2)
1 0 0 0 0 0 0 1 0 1 2 0 5 1 1 (Q2) â (A)
1 0 0 1 0 0 0 1 1 0 2 4 6 1 1 (A) â (Q3)
1 0 0 0 0 0 0 1 1 0 2 0 6 1 1 (Q3) â (A)
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 (PC) â (PC) + 1
0 0 0 0 0 0 0 0 1 0 0 0 2 1 1 Transition to clock operating mode
POF2
0 0 0 0 0 0 1 0 0 0 0 0 8 1 1 Transition to RAM back-up mode
EPOF
SNZP
0001011011
0000000011
05B 1
003 1
1 POF, POF2 instructions valid
1 (P) = 1 ?
WRST
1 0 1 0 1 0 0 0 0 0 2 A 0 1 1 (WDF1) = 1 ?
After skipping, (WDF1) â 0
DWDT
1 0 1 0 0 1 1 1 0 0 2 9 C 1 1 Stop of watchdog timer function enabled
RBK*
0 0 0 1 0 0 0 0 0 0 0 4 0 1 1 When TABP p instruction is executed, P6 â 0
SBK*
0 0 0 1 0 0 0 0 0 1 0 4 1 1 1 When TABP p instruction is executed, P6 â 1
SVDE
1 0 1 0 0 1 0 0 1 1 2 9 3 1 1 At power down mode, voltage drop detection
circuit valid
Note: * (SBK, RBK) cannot be used in the M34524M8.
The pages which can be referred by the TABP instruction after the SBK instruction is executed are
64 to 95 in the M34524MC.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1-146
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