4524_M Datasheet, PDF (166/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.1 I/O pins
2.1 I/O pins
The 4524 Group has twenty-eight I/O pins and three output pins.
Port P2 is also used as analog input pins AIN0–AIN3.
Port P3 is also used as analog input pins AIN4–AIN7.
Ports D4–D6 are also used as Serial I/O pins SIN, SOUT, SCK.
Port D7 is also used as CNTR0 I/O pin.
Port D8 is also used as INT0 input pin.
Port D9 is also used as INT1 input pin.
Port C is also used as CNTR1 I/O pin.
This section describes each port I/O function, related registers, application example using each port function
and notes.
2.1.1 I/O ports
(1) Port P0
Port P0 is a 4-bit I/O port.
Port P0 has the key-on wakeup function which turns ON/OFF with register K0 and pull-up transistor
which turns ON/OFF with register PU0.
q Input
In the following conditions, the pin state of port P0 is transferred as input data to register A when
the IAP0 instruction is executed.
• Set bit FR00 or bit FR01 of register FR0 to “0” according to the port to be used.
• Set the output latch of specified port P0i (i=0, 1, 2 or 3) to “1” with the OP0A instruction.
If FR00 or FR01 is “0” and the output latch is “0”, “0” is output to specified port P0.
If FR00 or FR01 is “1”, the output latch value is output to specified port P0.
q Output
The contents of register A is set to the output latch with the OP0A instruction, and is output to port
P0.
N-channel open-drain or CMOS can be selected as the output structure of port P0 in 2 bits unit
by setting FR00 or FR01.
(2) Port P1
Port P1 is a 4-bit I/O port.
Port P1 has the key-on wakeup function which turns ON/OFF with register K1 and pull-up transistor
which turns ON/OFF with register PU1.
q Input
In the following conditions, the pin state of port P1 is transferred as input data to register A when
the IAP1 instruction is executed.
• Set bit FR02 or bit FR03 of register FR0 to “0” according to the port to be used.
• Set the output latch of specified port P1i (i=0, 1, 2 or 3) to “1” with the OP1A instruction.
If FR02 or FR03 is “0” and the output latch is “0”, “0” is output to specified port P1.
If FR02 or FR03 is “1”, the output latch value is output to specified port P1.
q Output
The contents of register A is set to the output latch with the OP1A instruction, and is output to port
P1.
N-channel open-drain or CMOS can be selected as the output structure of port P1 in 2 bits unit
by setting FR02 or FR03.
Rev.2.00 Aug, 06 2004
2-2
REJ09B0107-0200Z