4524_M Datasheet, PDF (222/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.5 Serial I/O
(5) Serial I/O mode register J1
Table 2.5.3 shows the serial I/O mode register J1.
Set the contents of this register through register A with the TJ1A instruction.
In addition, the TAJ1 instruction can be used to transfer the contents of register J1 to register A.
Table 2.5.3 Serial I/O mode register J1
Serial I/O control register J1
at reset : 00002 at power down : state retained R/W
J13 J12
Synchronous clock
J13
0 0 Instruction clock (INSTCK) divided by 8
Serial I/O synchronous clock _{0 1 Instruction clock (INSTCK) divided by 4}
selection bits
J12
1 0 Instruction clock (INSTCK) divided by 2
1 1 External clock (SCK input)
J11 J10
Port function
J11 _{Serial I/O port function selection 0 0 D6, D5, D4 selected/SCK, SOUT, SIN not selected}
bits
J10
0 1 SCK, SOUT, D4 selected/D6, D5, SIN not selected
1 0 _{SCK, D5, SIN selected/D6, SOUT, D4 not selected}
1 1 _{SCK, SOUT, SIN selected/D6, D5, D4 not selected}
Note: “R” represents read enabled, and “W” represents write enabled.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-58