4524_M Datasheet, PDF (293/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPENDIX
3.3 List of precautions
(7) Port D8/INT0 pin
When the power down mode is used by clearing the bit 3 of register I1 to “0” and setting the input
of INT0 pin to be disabled, be careful about the following note.
• When the input of INT0 pin is disabled (register I13 = “0”), clear bit 0 of register K2 to “0” to
invalidate the key-on wakeup before system goes into the power down mode.
(8) Port D9/INT1 pin
When the power down mode is used by clearing the bit 3 of register I2 to “0” and setting the input
of INT1 pin to be disabled, be careful about the following note.
• When the input of INT1 pin is disabled (register I23 = “0”), clear bit 2 of register K2 to “0” to
invalidate the key-on wakeup before system goes into the power down mode.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
3-39