4524_M Datasheet, PDF (25/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
HARDWARE
PORT BLOCK DIAGRAM
Register Y
Decoder
Skip decision
(SZD instruction)
SD instruction
RD instruction
CLD
instruction
S
RQ
FR23
W60
0
1
Underflow signal divided by 2
of timer 1 or timer 2
W11
W10
Clock (input) for timer 1 event count
Timer 1 count start synchronous circuit input
Key-on wakeup
External 0 interrupt
Register Y
Decoder
CLD
instruction
SD instruction
RD instruction
(Note 3)
External 0 interrupt
circuit
S
RQ
Timer 3 count start synchronous circuit input
Key-on wakeup
External 1 interrupt
Register Y
Decoder
SD instruction
CLD
instruction
RD instruction
(Note 3)
External 1 interrupt
circuit
S
RQ
(Note 1)
D7/CNTR0
(Note 2)
(Note 1)
D8/INT0
(Note 2)
(Note 1)
D9/INT1
(Note 2)
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
3: As for details, refer to the description of external interrupt circuit.
Port block diagram (3)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1-12