4524_M Datasheet, PDF (173/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.1 I/O pins
(9) Port output structure control register FR0
Table 2.1.9 shows the port output structure control register FR0.
Set the contents of this register through register A with the TFR0A instruction.
Table 2.1.9 Port output structure control register FR0
Port output structure control register FR0 at reset : 00002 at power down : state retained
W
Ports P12, P13
FR03
output structure selection bit
Ports P10, P11
FR02
output structure selection bit
Ports P02, P03
FR01
output structure selection bit
Ports P01, P00
FR00
output structure selection bit
Note: “W” represents write enabled.
0 N-channel open-drain output
1 CMOS output
0 N-channel open-drain output
1 CMOS output
0 N-channel open-drain output
1 CMOS output
0 N-channel open-drain output
1 CMOS output
(10) Port output structure control register FR1
Table 2.1.10 shows the port output structure control register FR1.
Set the contents of this register through register A with the TFR1A instruction.
Table 2.1.10 Port output structure control register FR1
Port output structure control register FR1 at reset : 00002 at power down : state retained
W
Port D3
FR13
output structure selection bit
Port D2
FR12
output structure selection bit
Port D1
FR11
output structure selection bit
Port D0
FR10
output structure selection bit
Note: “W” represents write enabled.
0 N-channel open-drain output
1 CMOS output
0 N-channel open-drain output
1 CMOS output
0 N-channel open-drain output
1 CMOS output
0 N-channel open-drain output
1 CMOS output
Rev.2.00 Aug, 06 2004
2-9
REJ09B0107-0200Z