4524_M Datasheet, PDF (169/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.1 I/O pins
2.1.2 Related registers
(1) Timer control register W3
Table 2.1.1 shows the timer control register W3.
Set the contents of this register through register A with the TW3A instruction.
The contents of register W3 is transferred to register A with the TAW3 instruction.
Table 2.1.1 Timer control register W3
Timer control register W3
at reset : 00002 at power down : state retained R/W
Timer 3 count auto-stop circuit 0 Timer 3 count auto-stop circuit not selected
W33
selection bit (Note 2)
1 Timer 3 count auto-stop circuit selected
W32 Timer 3 control bit
0 Stop (state retained)
1 Operating
W31W30
Count source
W31
W30
0
Timer 3 count source selection
0
bits (Note 3)
1
0 PWM signal (PWMOUT)
1 Prescaler output (ORCLK)
0 Timer 2 underflow signal (T2UDF)
1 1 CNTR1 input
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 3 count start synchronous circuit is selected (I20=“1”).
3: Port C output is invalid when CNTR1 input is selected for the timer 3 count source.
4: When setting the port, W33–W32 are not used.
(2) Timer control register W4
Table 2.1.2 shows the timer control register W4.
Set the contents of this register through register A with the TW4A instruction.
The contents of register W4 is transferred to register A with the TAW4 instruction.
Table 2.1.2 Timer control register W4
Timer control register W4
at reset : 00002 at power down : state retained R/W
W43 CNTR1 output control bit
0 CNTR1 output invalid
1 CNTR1 output valid
PWM signal “H” interval
W42
expansion function control bit
0 PWM signal “H” interval expansion function invalid
1 PWM signal “H” interval expansion function valid
W41 Timer 4 control bit
0 Stop (state retained)
1 Operating
0 XIN input
W40 Timer 4 count source selection bit
1 Prescaler output (ORCLK) divided by 2
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When setting the port, W42–W40 are not used.
Rev.2.00 Aug, 06 2004
2-5
REJ09B0107-0200Z