4524_M Datasheet, PDF (171/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.1 I/O pins
(5) A/D control register Q2
Table 2.1.5 shows the A/D control register Q2.
Set the contents of this register through register A with the TQ2A instruction.
The contents of register Q2 is transferred to register A with the TAQ2 instruction.
Table 2.1.5 A/D control register Q2
AD control register Q2
at reset : 00002 at power down : state retained
0 P23
Q23 P23/AIN3 pin function selection bit
1 AIN3
0 P22
Q22 P22/AIN2 pin function selection bit
1 AIN2
0 P21
Q21 P21/AIN1 pin function selection bit
1 AIN1
0 P20
Q20 P20/AIN0 pin function selection bit
1 AIN0
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: In order to select AIN3–AIN0, set register Q1 after setting register Q2.
(6) A/D control register Q3
Table 2.1.6 shows the A/D control register Q3.
Set the contents of this register through register A with the TQ3A instruction.
The contents of register Q3 is transferred to register A with the TAQ3 instruction.
Table 2.1.6 A/D control register Q3
AD control register Q3
at reset : 00002 at power down : state retained
0 P33
Q33 P33/AIN7 pin function selection bit
1 AIN7
0 P32
Q32 P32/AIN6 pin function selection bit
1 AIN6
0 P31
Q31 P31/AIN5 pin function selection bit
1 AIN5
0 P30
Q30 P30/AIN4 pin function selection bit
1 AIN4
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: In order to select AIN7–AIN4, set register Q1 after setting regsiter Q3.
R/W
R/W
Rev.2.00 Aug, 06 2004
2-7
REJ09B0107-0200Z