4524_M Datasheet, PDF (236/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.7 Reset
2.7 Reset
System reset is performed by applying “L” level to the RESET pin for 1 machine cycle or more when the
following conditions are satisfied:
q the value of supply voltage is the minimum value or more of the recommended operating conditions.
Then when “H” level is applied to RESET pin, the program starts from address 0 in page 0 after elapsing
of the internal oscillation stabilizing time (On-chip oscillator (internal oscillator) clock is counted for 5400 to
5424 times). Figure 2.7.2 shows the oscillation stabilizing time.
2.7.1 Reset circuit
The 4524 Group has the voltage drop detection circuit.
(1) Power-on reset
Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset
circuit. When the built-in power-on reset circuit is used, the time for the supply voltage to rise from
0 V to the minimum rating value of the recommended operating conditions must be set to 100 µs or
less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and VSS at the
shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the
minimum rating value of the recommended operating conditions.
100 µs or less
VDD (Note 3)
(Note 1)
(Note 2)
RESET pin
(Note 1)
Pull-up transistor
Internal reset signal
Power-on reset circuit
Voltage drop detection circuit
Watchdog reset signal
Power-on reset circuit output
Internal reset signal
WEF
Reset
state
Power-on Reset released
Notes 1:
This symbol represents a parasitic diode.
2: Applied potential to RESET pin must be VDD or less.
3: Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
Fig. 2.7.1 Structure of reset pin and its peripherals, and power-on reset operation
Reset input
1 machine cycle or more
On-chip oscillator (internal oscillator) is
counted 5400 to 5424 times. (Note 2)
0.85VDD
RESET
0.3VDD
Program starts
(address 0 in page 0)
(Note 1)
Notes 1: Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
2: It depends on the internal state at reset.
Fig. 2.7.2 Oscillation stabilizing time after system is released from reset
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-72