4524_M Datasheet, PDF (243/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.9 Power down
Table 2.9.1 Functions and states retained at power down mode
Function
Program counter (PC), registers A, B,
Power down mode
Clock operating
RAM back-up
✕
✕
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
Interrupt control registers V1, V2
O
O
✕
✕
Interrupt control registers I1 to I3
O
O
Selected oscillation circuit
Clock control register MR
Timer 1 to timer 4 functions
O
O
(Note 3)
O
O
(Note 3)
Timer 5 function
Timer LC function
Watchdog timer function
Timer control registers PA, W4
O
O
✕ (Note 4)
✕
O
(Note 3)
✕ (Note 4)
✕
Timer control registers W1 to W3, W5, W6
Serial I/O function
Serial I/O control register J1
A/D function
O
O
✕
✕
O
O
✕
✕
A/D control registers Q1 to Q3
O
O
LCD display function
LCD control registers L1, L2
Voltage drop detection circuit
O
O
(Note 6)
(Note 5)
O
(Note 6)
Port level
Pull-up control registers PU0, PU1
Key-on wakeup control registers K0 to K2
(Note 7)
O
O
(Note 7)
O
O
Port output format control registers FR0 to FR3
External interrupt request flags (EXF0, EXF1)
Timer interrupt request flags (T1F to T4F)
Timer interrupt request flag (T5F)
A/D conversion completion flag (ADF)
Serial I/O transmit/receive completion flag SIOF
Interrupt enable flag (INTE)
Watchdog timer flags (WDF1, WDF2)
Watchdog timer enable flag (WEF)
O
✕
(Note 3)
O
✕
✕
✕
✕ (Note 4)
✕ (Note 4)
O
✕
(Note 3)
O
✕
✕
✕
✕ (Note 4)
✕ (Note 4)
Notes 1: “O” represents that the function can be retained, and “✕” represents that the function is initialized.
Registers and flags other than the above are undefined at power down, and set an initial value
after returning.
2: The stack pointer (SP) points the level of the stack register and is initialized to “7” at power down.
3: The state of the timer is undefined.
4: Initialize the watchdog timer flag WDF1 with the WRST instruction, and then go into the power down state.
5: LCD is turned off.
6: When the SVDE instruction is executed and the “H“ level is applied to the VDCE pin, this function
is valid at power down.
7: In the power down mode, C/CNTR1 pin outputs “L” level. However, when the CNTR input is
selected (W11, W10=“11”), C/CNTR1 pin is in an input enabled state (output=high-impedance).
Other ports retain their respective output levels.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-79