4524_M Datasheet, PDF (186/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.2 Interrupts
2.2.3 Interrupt application examples
(1) External 0 interrupt
The INT0 pin is used for external 0 interrupt, of which valid waveforms can be chosen, which can
recognize the change of falling edge (“H”→“L”), rising edge (“L”→“H”) and both edges (“H”→“L” or
“L”→“H”).
Outline: An external 0 interrupt can be used by dealing with the falling edge (“H”→“L”), rising edge
(“L”→“H”) and both edges (“H”→“L” or “L”→“H”) as a trigger.
Specifications: An interrupt occurs by the change of an external signals edge (“H”→“L” or “L”→“H”).
Figure 2.2.1 shows an operation example of an external 0 interrupt, and Figure 2.2.2 shows a setting
example of an external 0 interrupt.
(2) External 1 interrupt
The INT1 pin is used for external 1 interrupt, of which valid waveforms can be chosen, which can
recognize the change of falling edge (“H”→“L”), rising edge (“L”→“H”) and both edges (“H”→“L” or
“L”→“H”).
Outline: An external 1 interrupt can be used by dealing with the falling edge (“H”→“L”), rising edge
(“L”→“H”) and both edges (“H”→“L” or “L”→“H”) as a trigger.
Specifications: An interrupt occurs by the change of an external signals edge (“H”→“L” or “L”→“H”).
Figure 2.2.3 shows an operation example of an external 1 interrupt, and Figure 2.2.4 shows a setting
example of an external 1 interrupt.
(3) Timer 1 interrupt
Constant period interrupts by a setting value to timer 1 can be used.
Outline: The constant period interrupts by the timer 1 underflow signal can be used.
Specifications: Timer 1 divides the system clock frequency = 2.0 MHz, and the timer 1 interrupt
occurs every 0.25 ms.
Figure 2.2.5 shows a setting example of the timer 1 constant period interrupt.
(4) Timer 2 interrupt
Constant period interrupts by a setting value to timer 2 can be used.
Outline: The constant period interrupts by the timer 2 underflow signal can be used.
Specifications: Timer 2 and prescaler divide the system clock frequency (= 4.0 MHz), and the timer
2 interrupt occurs every 1 ms.
Figure 2.2.6 shows a setting example of the timer 2 constant period interrupt.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
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