4524_M Datasheet, PDF (187/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.2 Interrupts
(5) Timer 3 interrupt
Constant period interrupts by a setting value to timer 3 can be used.
Outline: The constant period interrupts by the timer 3 underflow signal can be used.
Specifications: Prescaler and timer 3 divide the system clock frequency = 4.0 MHz, and the timer
3 interrupt occurs every 1 ms.
Figure 2.2.7 shows a setting example of the timer 3 constant period interrupt.
(6) Timer 4 interrupt
Constant period interrupts by a setting value to timer 4 can be used.
Outline: The constant period interrupts by the timer 4 underflow signal can be used.
Specifications: Timer 4 and prescaler divide the system clock frequency (= 4.0 MHz), and the timer
4 interrupt occurs every 50 ms.
Figure 2.2.8 shows a setting example of the timer 4 constant period interrupt.
(7) Timer 5 interrupt
Timer 5 is a fixed dividing frequency timer. Constant period interrupts which count source is divided
2¹³, 2¹⁴, 2¹⁵ or 2¹⁶ can be used.
Outline: The constant period interrupts by the timer 5 underflow signal can be used.
Specifications: Timer 5 divides the sub-clock frequency ((f(XCIN) = 32.768 kHz), and the timer 5
interrupt occurs every 500 ms.
Figure 2.2.9 shows a setting example of the timer 5 constant period interrupt.
“H”
D8/INT0
“L”
“H”
D8/INT0
“L”
An interrupt occurs after the valid waveform “falling” is detected.
An interrupt occurs after the valid waveform “rising” is detected.
Fig. 2.2.1 External 0 interrupt operation example
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
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