4524_M Datasheet, PDF (207/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.3 Timers
➀ Disable Interrupts
Timer 2 interrupt is temporarily disabled.
Interrupt enable flag INTE
Interrupt control register V1
0
b3
b0
0 ✕✕✕
All interrupts disabled [DI]
b3: Timer 2 interrupt occurrence disabled [TV1A]
↓
➁ Stop Timer and Prescaler Operation
Timer 2 and prescaler are temporarily stopped.
Timer 2 count source and CNTR0 output are selected.
b3
b0
Timer control register W2 1 0 0 1
b0
Timer control register PA
0
[TW2A]
b3: Timer 2 underflow signal divided by 2 selected for
CNTR0 output
b2: Timer 2 stop
b1, b0: Prescaler output (ORCLK) selected for
Timer 2 count source
Prescaler stop [TPAA]
↓
➂ Set CNTR0 Output
The output structure of the CNTR0 pin is set to N-channel open-drain output.
Port output structure control register FR2
b3
b0
0 ✕ ✕ ✕ b3: N-channel open-drain output selected [TFR2A]
Timer control register W6
b3
b0
✕ ✕ ✕ 1 b0: CNTR0 output port set [TW6A]
↓
➃ Set Timer Value and Prescaler Value
Timer 2 and prescaler count times are set. (The formula is shown *A below.)
Timer 2 reload register R2 “2916”
Timer count value 41 set [T2AB]
Prescaler reload register RPS “0316”
Prescaler count value 3 set [TPSAB]
↓
➄ Clear Interrupt Request
Timer 2 interrupt activated condition is cleared.
Timer 2 interrupt request flag T2F 0
Timer 2 interrupt activated condition cleared [SNZT2]
↓
( ) Note when the interrupt request is cleared
When ➄ is executed, considering the skip of the next instruction according to the interrupt request flag T2F,
insert the NOP instruction after the SNZT2 instruction.
↓
➅ Start Timer Operation and Prescaler Operation
Timer 2 and prescaler temporarily stopped are restarted.
b3
b0
Timer control register W2 1 1 0 1
b0
Timer control register PA
1
b2: Timer 2 operation start [TW2A]
Prescaler start [TPAA]
↓
~ Enable Interrupts
The Timer 2 interrupt which is temporarily disabled is enabled.
Interrupt control register V1
b3
b0
1 ✕ ✕ ✕ b3: Timer 2 interrupt occurrence enabled [TV1A]
Interrupt enable flag INTE 1
All interrupts enabled [EI]
↓
Buzzer ou...tput start
↓
➇ Stop CNTR0 Output
CNTR0 I/O port is set to CNTR0 input port and is set to be high-impedance state.
b3
b0
Register Y 0 1 1 1 Specify bit position of port D [TYA]
Port D7 output latch 1
Set to input [SD]
Timer control register W6
b3
b0
✕ ✕ ✕ 0 b0: Set to CNTR0 input port [TW6A]
*A: The prescaler count value and timer 2 count value to make the underflow occur every 125 µs are set as follows.
125 µs ≅ (4.0 MHz)^-1 ✕ 3 ✕ (3 +1) ✕ (41 +1)
System clock Instruction Presclaer
Timer 2 count value
clock
count value
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Fig. 2.3.5 CNTR0 output setting example
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
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