4524_M Datasheet, PDF (179/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.1 I/O pins
Table 2.1.16 Connections of unused pins
Pin
Connection
Usage condition
XIN
Connect to VSS. Internal oscillator is selected (CMCK and CRCK instructions are not executed.) (Note 1)
Sub-clock input is selected for system clock (MR0=1).
(Note 2)
XOUT
Open.
Internal oscillator is selected (CMCK and CRCK instructions are not executed.) (Note 1)
RC oscillator is selected (CRCK instruction is executed)
External clock input is selected for main clock (CMCK instruction is executed). (Note 3)
Sub-clock input is selected for system clock (MR0=1).
(Note 2)
XCIN
Connect to VSS. Sub-clock is not used.
XCOUT
Open.
Sub-clock is not used.
D0–D3
Open.
Connect to VSS. N-channel open-drain is selected for the output structure.
(Note 4)
D4/SIN
Open.
SIN pin is not selected.
Connect to VSS. N-channel open-drain is selected for the output structure.
D5/SOUT
Open.
Connect to VSS. N-channel open-drain is selected for the output structure.
D6/SCK
Open.
SCK pin is not selected.
Connect to VSS. N-channel open-drain is selected for the output structure.
D7/CNTR0 Open.
CNTR0 input is not selected for timer 1 count source.
Connect to VSS. N-channel open-drain is selected for the output structure.
D8/INT0
Open.
“0” is set to output latch.
Connect to VSS.
D9/INT1
Open.
“0” is set to output latch.
Connect to VSS.
C/CNTR1 Open.
CNTR1 input is not selected for timer 3 count source.
P00–P03
Open.
The key-on wakeup function is not selected.
(Note 4)
Connect to Vss. N-channel open-drain is selected for the output structure.
(Note 5)
The pull-up function is not selected.
(Note 4)
The key-on wakeup function is not selected.
(Note 4)
P10–P13
Open.
The key-on wakeup function is not selected.
(Note 4)
Connect to Vss. N-channel open-drain is selected for the output structure.
(Note 5)
The pull-up function is not selected.
(Note 4)
The key-on wakeup function is not selected.
(Note 4)
P20/AIN0–
Open.
P23/AIN3
Connect to Vss.
P30/AIN4–
Open.
P33/AIN7
Connect to Vss.
P40–P43
Open.
Connect to Vss. N-channel open-drain is selected for the output structure.
(Note 4)
COM0–COM3 Open.
VLC3/SEG0 Open.
SEG0 pin is selected.
VLC2/SEG1 Open.
SEG1 pin is selected.
VLC1/SEG2 Open.
SEG2 pin is selected.
SEG3–SEG19 Open.
Notes 1: When the CMCK and CRCK instructions are not executed, the internal oscillation (on-chip oscillator)
is selected for main clock.
2: When sub-clock (XCIN) input is selected (MR0 = 1) for the system clock by setting “1” to bit 1 (MR1)
of clock control register MR, main clock is stopped.
3: Select the ceramic resonance by executing the CMCK instruction to use the external clock input
for the main clock.
4: Be sure to select the output structure of ports D0–D3 and P40–P43 and the pull-up function and
key-on wakeup function of P00–P03 and P10–P13 with every one port. Set the corresponding bits
of registers for each port.
5: Be sure to select the output structure of ports P00–P03 and P10–P13 with every two ports. If only
one of the two pins is used, leave another one open.
(Note when connecting unused pins to VSS or VDD)
q Connect the unused pins to VSS or VDD using the thickest wire at the shortest distance against noise.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-15