4524_M Datasheet, PDF (196/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.2 Interrupts
2.2.4 Notes on use
(1) Setting of INT0 interrupt valid waveform
Set a value to the bit 2 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction.
Depending on the input state of D8/INT0 pin, the external interrupt request flag (EXF0) may be set
to “1” when the bit 2 of register I1 is changed.
(2) Setting of INT0 pin input control
Set a value to the bit 3 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction.
Depending on the input state of D8/INT0 pin, the external interrupt request flag (EXF0) may be set
to “1” when the bit 3 of register I1 is changed.
(3) Setting of INT1 interrupt valid waveform
Set a value to the bit 2 of register I2, and execute the SNZ1 instruction to clear the EXF1 flag to
“0” after executing at least one instruction.
Depending on the input state of D9/INT1 pin, the external interrupt request flag (EXF1) may be set
to “1” when the bit 2 of register I2 is changed.
(4) Setting of INT1 pin input control
Set a value to the bit 3 of register I2, and execute the SNZ1 instruction to clear the EXF1 flag to
“0” after executing at least one instruction.
Depending on the input state of D9/INT1 pin, the external interrupt request flag (EXF1) may be set
to “1” when the bit 3 of register I2 is changed.
(5) Multiple interrupts
Multiple interrupts cannot be used in the 4524 Group.
(6) Notes on interrupt processing
When the interrupt occurs, at the same time, the interrupt enable flag INTE is cleared to “0” (interrupt
disable state). In order to enable the interrupt at the same time when system returns from the
interrupt, write EI and RTI instructions continuously.
(7) D8/INT0 pin
When the external interrupt input pin INT0 is used, set the bit 3 of register I1 to “1”.
Even in this case, port D8 output function is valid.
Also, the EXF0 flag is set to “1” when bit 3 of register I1 is set to “1” by input of a valid waveform
(valid waveform causing external 0 interrupt) even if it is used as an output port D8.
(8) D9/INT1 pin
When the external interrupt input pin INT1 is used, set the bit 3 of register I2 to “1”.
Even in this case, port D9 output function is valid.
Also, the EXF1 flag is set to “1” when bit 3 of register I2 is set to “1” by input of a valid waveform
(valid waveform causing external 1 interrupt) even if it is used as an output port D9.
(9) POF instruction, POF2 instruction
When the POF or POF2 instruction is executed continuously after the EPOF instruction, system
enters the power down state.
Note that system cannot enter the power down state when executing only the POF or POF2 instruction.
Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction
and the POF or POF2 instruction continuously.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
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