4524_M Datasheet, PDF(183/310 Page) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

4524_M Datasheet, PDF (183/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

◁

4524 Group

APPLICATION

2.2 Interrupts

2.2.2 Related registers

(1) Interrupt enable flag (INTE)

The interrupt enable flag (INTE) controls whether the every interrupt enable/disable.

Interrupts are enabled when INTE flag is set to â1â with the EI instruction and disabled when INTE

flag is cleared to â0â with the DI instruction.

When any interrupt occurs while the INTE flag is â1â, the INTE flag is automatically cleared to â0,â

so that other interrupts are disabled until the EI instruction is executed.

Note: The interrupt enabled with the EI instruction is performed after the EI instruction and one more

instruction.

(2) Interrupt request flag

The activated condition for each interrupt is examined. Each interrupt request flag is set to â1â when

the activated condition is satisfied, even if the interrupt is disabled by the INTE flag or its interrupt

enable bit.

Each interrupt request flag is cleared to â0â when either;

â¢an interrupt occurs, or

â¢the next instruction is skipped with a skip instruction.

(3) Interrupt control register V1

Table 2.2.1 shows the interrupt control register V1.

Set the contents of this register through register A with the TV1A instruction.

In addition, the TAV1 instruction can be used to transfer the contents of register V1 to register A.

Table 2.2.1 Interrupt control register V1

Interrupt control register V1

at reset : 00002

at power down : 00002

R/W

V13 Timer 2 interrupt enable bit

0 Interrupt disabled (SNZT2 instruction is valid)

1 Interrupt enabled (SNZT2 instruction is invalid) (Note 2)

V12 Timer 1 interrupt enable bit

0 Interrupt disabled (SNZT1 instruction is valid)

1 Interrupt enabled (SNZT1 instruction is invalid) (Note 2)

V11 External 1 interrupt enable bit

0 Interrupt disabled (SNZ1 instruction is valid)

1 Interrupt enabled (SNZ1 instruction is invalid) (Note 2)

V10 External 0 interrupt enable bit

0 Interrupt disabled (SNZ0 instruction is valid)

1 Interrupt enabled (SNZ0 instruction is invalid) (Note 2)

Notes 1: âRâ represents read enabled, and âWâ represents write enabled.

2: These instructions are equivalent to the NOP instruction.

Rev.2.00 Aug, 06 2004

REJ09B0107-0200Z

2-19

▷