DS92UT16 Datasheet, PDF (90/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
OBSOLETE
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
Test Features
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TEST STRUCTURES
The DS92UT16 device has the following test structures in place.
• Internal SCAN (manufacturing test only)
• RAM BIST (manufacturing test only)
• Boundary SCAN
As shown, the device has a AP controller which was generated using the LOGICVISION tool suite. This AP
controller is used to configure the device for scan testing, RAM BIST and Boundary Scan. The Instruction
Register is shown in Figure 23. Bits 12–18 are not used. A more detailed description of the operation of the TAP
controller can be found in the LOGICVISION document: Adding Logic Test—A Hardware Reference July 2000.
NOTE
The Internal SCAN and RAM BIST functions are not user accessible. Therefore, the
device user should never assert the Test_se pin
Figure 23. LOGICVISION TAP Instruction Register
The TAP controller contains a device ID register which holds the device identification. Figure 24 shows the
makeup of the device ID register and the device ID value for the DS92UT16 device.
DEVICE ID = 0FC2801F
Figure 24. Device Identification Register
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