DS92UT16 Datasheet, PDF (18/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
OBSOLETE
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
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UTOPIA Interface Operation
This section describes the operation of the UTOPIA Interface of the DS92UT16. The UTOPIA interface mode of
operation is defined in the UTOPIA Configuration (UCFG) register described in UTOPIA
CONFIGURATION—0xA0 UCFG. The format of the PDU cells carried over this interface is defined in the PDU
Configuration (PDUCFG) register described in PDU CONFIGURATION—0x05 PDUCFG.
The interface can operate in ATM layer mode or PHY layer mode. When operating as a Level 2 ATM layer
interface, the protocol can be extended to cope with up to 248 PHY ports rather than the maximum 31 allowed
by the standard Level 2 definition. This Extended Level 2 mode is achieved with eight CLAV and eight ENB
signals.
On power up the device defaults to ATM layer mode. To prevent potential contention on the Utopia interface
signals, all the Utopia pins which are bidirectional are configured as outputs in tri-state mode and the Utopia
interface block is disabled. The user must select the device operating mode, ATM layer or PHY layer, by writing
the appropriate value to the UMODE bit of the UCFG register before enabling the Utopia interface block and
releasing the Utopia interface pins. Enabling the Utopia interface and releasing the Utopia pins is achieved by
setting the UBDEN bit of the UCFG register.
UTOPIA BASIC LEVEL 2 MODE - 31 PORTS (Default Mode)
In UTOPIA Level 2 mode:
• 8-bit or 16-bit data buses are controlled by the BWIDTH bit of the UCFG register. In 8-bit mode only
U_TxData[7:0] and U_RxData[7:0] are valid; parity is calculated and checked only over these bits of the data
buses and the upper bits of the data buses are not used. In 16-bit mode of the full U_TxData[15:0] and
U_RxData[15:0] are valid and parity is calculated over all bits of the data buses.
• One ATM Layer can communicate with up to 31 PHY ports using the MPhy address busses U_TxAddr[4:0]
and U_RxAddr[4:0] and the control signals U_TxCLAV[0], U_RxCLAV[0], U_TxENB[0] and U_RxENB[0].
• U_TxCLAV[7:1], U_RxCLAV[7:1], U_TxENB[7:1] and U_RxENB[7:1] are not used.
• All Queues from 30 to 0 of the MTB may be used. There is one queue for each MPhy address so the use of
the queues will depend on the connected ports list defined by the UCPL3–UCPL0 registers.
• Uses the connected ports list defined by the UCPL3-UCPL0 registers. In ATM mode, these registers are used
to determine the ports that should be polled. In PHY mode, these registers are used to determine which
MPhy addresses the device should respond to during polling.
• The connected sub-port list defined in the UCSPL register is not used.
• The sub-port address location defined by USPAL and USPAM registers is not used.
• The CLAV mode bits CLVM[1:0] of the UCFG register should be defined as CLVM[1:0] = 00.
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