DS92UT16 Datasheet, PDF (64/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
OBSOLETE
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
RECEIVE PORT A LINK LABEL—0x20 RALL
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Table 40. RALL
7
RALL[7]
Type: Read only
6
RALL[6]
5
RALL[5]
4
RALL[4]
3
RALL[3]
2
RALL[2]
1
RALL[1]
0
RALL[0]
Software Lock: No
Reset Value: 0x00
The Receive Port A Link Label register contains the Link Trace Label byte received in TC6 on receive Port A.
Whenever the received link label changes value, the RALLC alarm bit in the RALA register is set, which will raise
an interrupt if the corresponding interrupt enable bit is set.
• RALL[7:0] Port A Received Link Trace Label byte contents.
RECEIVE PORT A EXPECTED LINK LABEL—0x21 RAELL
Table 41. RAELL
7
RAELL[7]
Type: Read only
6
RAELL[6]
5
RAELL[5]
4
RAELL[4]
3
RAELL[3]
2
RAELL[2]
1
RAELL[1]
0
RAELL[0]
Software Lock: No
Reset Value: 0x00
The Receive Port A Expected Link Label register defines the expected contents of the Link Trace Label byte
received in TC6 on receive Port A. If the actual received value, as stored in the RALL register is not the same as
the expected value defined here the RALLM alarm bit in the RALA register is set, which may raise a processor
interrupt if the corresponding interrupt enable is set.
• RAELL[7:0] Port A Expected Received Link Trace Label byte contents.
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