DS92UT16 Datasheet, PDF (59/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

OBSOLETE
DS92UT16
www.ti.com
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
ECC TRANSMIT BUFFER AND RECEIVE LVDS ALARMS—0x0A ETXRXA
Table 29. ETXRXA
7
6
5
Reserved Reserved Reserved
Type: Bits[3:1] Read only/Clear on Read
Bit[0] Read only
4
Reserved
3
LLOSC
2
LLOSA
1
LLOSB
0
ETXBR
Software Lock: No
Reset Value: 0x01
This register contains the status of the ECC transmit buffer and the LOCK signals from the two LVDS receive
ports. When set the LLOSA, LLOSB and LLOSC bits will raise an interrupt if the corresponding interrupt enable
bit is set.
• LLOSA Local Loss Of Signal on receive Port A. When set this will also clear all the bits in the Receive Port A
Remote Alarms register.
• LLOSB Local Loss Of Signal on receive Port B. When set this will also clear all the bits in the Receive Port B
Remote Alarms register.
• LLOSC Local Loss Of Signal Change. When set this indicates that there has been a change of value for
either LLOSA or LLOSB.
The ETXBR register bit indicates that the ECC transmit section has successfully transmitted the full ECC
message consisting of the 8 data bytes contained in registers ETXD7–ETXD0 and a new message can be
assembled and transmitted. This is a read only bit that the processor must examine before assembling a new
ECC message in the ETXD7–ETXD0 data registers.
If this bit is not set then any writes to ETXD7–ETXD0 will have no affect.
On reset the ETXBR will be set indicating a message can be assembled for transmission. The processor
assembles a message in the ETXD7–ETXD0 data registers. To send the message the processor simply sets the
ETXSD register bit. This clears the ETXBR bit which prevents write access to the ETXD7–ETXD0 registers so
that the message cannot be overwritten. When the far end ECC receiver indicates via the ECC signaling that the
message has been received successfully, then the near end ECC transmitter ETXSD bit is cleared and the
ETXBR bit is set. The ETXBR bit, when set, may raise a processor interrupt if the corresponding interrupt enable
is set. The processor can therefore detect that a message has been successfully transmitted either by the
interrupt or by polling the ETXBR bit.
Note that the ETXBR bit cannot be cleared on a read of this register but can only be cleared by setting the
ETXSD bit of the ETXSD register.
• ETXBR The ETXBR bit, when set, indicates that the current ECC message has been successfully transmitted
and a new message can be assembled. If this bit is not set, then the current message has not been received
at the far end and a new message cannot be assembled. The ETXBR bit is cleared by the setting of the
ETXSD bit. The ETXBR bit is set either by the far end successfully receiving a message or by the processor
clearing the ETXSD bit.
ECC Tx BUFFER AND Rx LVDS INTERRUPT ENABLES—0x0B ETXRXIE
Table 30. ETXRXIE
7
Reserved
Type: Read/Write
6
Reserved
5
Reserved
4
Reserved
3
LLOSCIE
2
LLOSAIE
1
LLOSBIE
0
ETXBRIE
Software Lock: No
Reset Value: 0x00
This register contains the interrupt enables for the alarms in the ETXRXA register. Set = interrupt enabled and
Clear = interrupt disabled.
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: DS92UT16
Submit Documentation Feedback
59