DS92UT16 Datasheet, PDF (46/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
OBSOLETE
www.ti.com
Figure 20. Intel Read Cycle
Table 16. Intel Read
No.
Parameter
1 Address Setup Time before Chip Select Low
2 Chip Select Setup before Write Low
3 Read Pulse Width⁽¹⁾⁽²⁾
4 Read Low to Data Low Impedance
5 Read Low to Valid Data⁽¹⁾⁽²⁾
6 Read High to Data High Impedance
7 Chip Select Hold after Read High
8 Address Hold after Read High
9 Read Recovery Time⁽¹⁾⁽³⁾
Min
0
0
8 cycles
0
0
1 cycle
Max
Units
ns
ns
10
ns
7 cycles + 15 ns
15
ns
ns
ns
(1) “Cycle” must be greater than or equal to the cycle time of the slowest DS92UT16 clock.
(2) When an LVDS receiver loses or gains “lock”, the recovered clock may stay high for up to 2.5 cycles.
If a processor access is in progress to one of the registers in either of the recovered clock domains,
then a READ will return the value of the last READ access, and a WRITE will not change the value of
the target register. To accommodate this possible gap in the clock, 3 cycles has been added to these
timings and they should therefore be regarded as worst case. If access time needs to be increased
and a system is robust enough to accept these possible incorrect accesses then 3 cycles can be
removed from these timings.
(3) A recovery time of 1 cycle is required between successive processor accesses.
46
Submit Documentation Feedback
Product Folder Links: DS92UT16
Copyright © 2002–2013, Texas Instruments Incorporated