DS92UT16 Datasheet, PDF (77/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

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RECEIVE PORT B BIP COUNT—0x74 to 0x76 RBBIPC2 to RBBIPC0
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
Table 67. RBBIPC2–RBBIPC0
7
6
RBBIPC2
0x74
RBBIPC2[7] RBBIPC2[6]
RBBIPC1
0x75
RBBIPC1[7] RBBIPC1[6]
RBBIPC0
0x76
RBBIPC0[7] RBBIPC0[6]
Type: Read only/Clear on Read
5
RBBIPC2[5]
RBBIPC1[5]
RBBIPC0[5]
4
RBBIPC2[4]
RBBIPC1[4]
RBBIPC0[4]
3
RBBIPC2[3]
RBBIPC1[3]
RBBIPC0[3]
2
RBBIPC2[2]
RBBIPC1[2]
RBBIPC0[2]
1
RBBIPC2[1]
RBBIPC1[1]
RBBIPC0[1]
0
RBBIPC2[0]
RBBIPC1[0]
RBBIPC0[0]
Software Lock: No
Reset Value: 0x00
The RBBIPC2, RBBIPC1 and RBBIPC0 registers contain the Port B received errored BIP count.
• RBBIPC2–RBBIPC0 This register must be read in the order of most significant byte RBBIPC2first and least
significant byte RBBIPC0 or the value read will not be valid. This counter will not roll-over from 0xFFFFFF to
0x000000 but will stick at 0xFFFFFF.
RECEIVE PORT B BIP THRESHOLD—0x77 to 0x79 RBBIPT2 to RBBIPT0
Table 68. RBBIPT2–RBBIPT0
7
RBBIPT2
0x77
RBBIPT2[7]
RBBIPT1
0x78
RBBIPT1[7]
RBBIPT0
0x79
RBBIPT0[7]
Type: Read/Write
6
RBBIPT2[6]
RBBIPT1[6]
RBBIPT0[6]
5
RBBIPT2[5]
RBBIPT1[5]
RBBIPT0[5]
4
RBBIPT2[4]
RBBIPT1[4]
RBBIPT0[4]
3
RBBIPT2[3]
RBBIPT1[3]
RBBIPT0[3]
2
RBBIPT2[2]
RBBIPT1[2]
RBBIPT0[2]
1
RBBIPT2[1]
RBBIPT1[1]
RBBIPT0[1]
0
RBBIPT2[0]
RBBIPT1[0]
RBBIPT0[0]
Software Lock: No
Reset Value: 0xFF
The RBBIPT2, RBBIPT1 and RBBIPT0 registers contain the Port B received erred BIP threshold. When the error
count RBBIPC equals the threshold RBBIPT, then the RBXBIP alarm will be set.
These registers should not be set to all zeroes.
• RBBIPT2–RBBIPT0 Most significant byte RBBIPT2 and least significant byte RBBIPT0.
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