DS92UT16 Datasheet, PDF (14/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
OBSOLETE
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
www.ti.com
CPU INTERFACE
The DS92UT16 contains a flexible microprocessor port capable of interfacing to any common system processor.
Via this port, the system software can customize the behavior of the device from the various options provided,
monitor the system performance, and activate diagnostic facilities such as loop-backs and LVDS BER testing.
In addition to an 8-bit address and 8-bit data bus plus the associated bus protocol control signals, the port
includes an open-drain interrupt signal. The device may assert this signal on the detection of various alarms
within the device, such as excessive HEC errors, ECC buffer full/empty, loss of lock etc. Any of the potential
internal sources of this interrupt may be inhibited individually via an interrupt mask.
A software lock mechanism is implemented to prevent spurious modification of some of the DS92UT16 software
accessible registers. A predefined UNLOCK write sequence is necessary to allow unrestricted software write
access to the DS92UT16. A corresponding LOCK write sequence will prevent any software write access to the
these registers. Read access is unrestricted except as noted in the next paragraph. See Table 9 for the LOCK
and UNLOCK sequences. Only device configuration registers such as PDU cell length, UTOPIA interface mode,
etc. are protected in this way. All other registers associated with the ECC, performance monitoring and interrupts
are always write accessible by the software except as noted in next paragraph. See SOFTWARE LOCK—0x00
to 0x01 SLK0 to SLK1.
Table 9. Software Lock Sequences
Meaning
Unlock Sequence
LOCK Sequence
Sequence
1st write
2nd write
1st write
2nd write
Address
0x00
0x01
0x00
0x01
Data
0x00
0xFF
0xDE
0xAD
Powering down a Receive Port inhibits access to the associated registers. This feature saves power when a
Receive Port is not in use. It allows re-reading the last value read from a register associated with that Receive
Port and disallows writing to registers. Receive Port A (RxA) in Power-down mode inhibits access to registers
described in RECEIVE PORT A LINK LABEL—0x20 RALL to RECEIVE PORT A BIT ERROR COUNT—0x43 to
0x45 RABEC2 to RABEC0. Receive Port B (RxB) in Power-down mode inhibits access to registers described in
RECEIVE PORT B LINK LABEL—0x60 RBLL to RECEIVE PORT B BIT ERROR COUNT—0x83 to 0x85
RBBEC2 to RBBEC0. The contents of these registers are not lost or altered in Power-down mode.
PERFORMANCE MONITORING AND ALARMS
The DS92UT16 provides a number of performance metrics and alarms to assist in equipment/network
management. The programmer can independently enable or disable these alarms to raise an interrupt. See
Performance Monitoring for a detailed description of the Performance Monitoring and General Alarms.
TEST INTERFACE
The IEEE 1149.1 JTAG [4.] port on the device provides access to the built-in test features such as boundary
SCAN, Internal SCAN and RAM BIST. It may be used to test the device individually or as part of a more
comprehensive circuit board or system test. (NOTE: The internal SCAN and RAM BIST functions are not
intended for user access. Therefore, the device user should never assert the Test_se pin.)
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