DS92UT16 Datasheet, PDF (87/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

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QUEUE FLUSH—0xD8 QFL
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
Table 88. QFL
7
Reserved
Type: Read/Write
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
FIBFL
0
MTBFL
Software Lock: Yes
Reset Value: 0x00
The Queue Flush register allows both the MTB and the FIB queues to be completely flushed. This removes all
PDU cells from either the MTB or FIB queue. The processor sets the appropriate bit in the QFL register to flush a
queue. When this has been completed, the hardware will clear the bit. So after setting a bit to flush a queue the
processor should poll the QFL register to determine when the flush has been completed.
• FIBFL When set, then a flush of the FIB queue is initiated and when clear, the FIB queue flush is completed
and the queue is now in normal operation.
• MTBFL When set, then a flush of the MTB queue is initiated and when clear, the MTB queue flush is
completed and the queue is now in normal operation.
MTB QUEUE OVERFLOW—0xD9 to 0xDC MTBQOV3 to MTBQOV0
Table 89. MTBQOV3–MTBQOV0
7
6
5
4
3
2
1
0
MTBQOV3
0xD9
Reserved MTBQOV3[6] MTBQOV3[5] MTBQOV3[4] MTBQOV3[3] MTBQOV3[2] MTBQOV3[1] MTBQOV3[0]
MTBQT29
0xDA
MTBQOV2[7] MTBQOV2[6] MTBQOV2[5] MTBQOV2[4] MTBQOV2[3] MTBQOV2[2] MTBQOV2[1] MTBQOV2[0]
MTBQOV1
0xDB
MTBQOV1[7] MTBQOV1[6] MTBQOV1[5] MTBQOV1[4] MTBQOV1[3] MTBQOV1[2] MTBQOV1[1] MTBQOV1[0]
MTBQOV0
0xDC
MTBQOV0[7] MTBQOV0[6] MTBQOV0[5] MTBQOV0[4] MTBQOV0[3] MTBQOV0[2] MTBQOV0[1] MTBQOV0[0]
Type: Read only/Clear on Read
Software Lock: No
Reset Value: 0x00
The MTBQOV3, MTBQOV2, MTBQOV1 and MTBQOV0 registers indicate the overflow status of the thirty-one
queues in the MTB. If a queue has filled to its threshold defined in the MTBQT31–MTBQT0 registers, and an
attempt is made to write another cell to the queue, then the overflow bit for that queue will be set in these
registers. These bits reflect that an attempt has been made to write to an already full queue and may be used as
an indication of problems with the Flow Control mechanism. Up to seven additional cells will be accepted into the
queue before a hard overflow occurs. Once the threshold value plus seven cells has been exceeded any
additional cells will be rejected and discarded automatically. A subsequent read of a cell from the specific queue
out over the Utopia interface will be successful, and will clear the overflow bit in this register once the number of
cells in the queue is below the threshold. If any bit in the MTBQOV3–MTBQOV0 registers is set then the
MTBSOVA bit of the UAA register will be set and may raise an interrupt.
• MTBQOV3–MTBQOV0 MTBQOV3[6] corresponds to queue 31 and MTBQOV0[0] corresponds to queue 0.
When a bit is set, then there was an attempt to overflow the corresponding queue.
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