DS92UT16 Datasheet, PDF (71/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

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DS92UT16
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SNOS992E – JANUARY 2002 – REVISED APRIL 2013
RECEIVE PORT A UP2DOWN LOOPBACK CELL COUNT—0x3E RAU2DLBC
Table 54. RAU2DLBC
7
6
5
4
RAU2DLBC[7] RAU2DLBC[6] RAU2DLBC[5] RAU2DLBC[4]
Type: Read only/Clear on Read
3
RAU2DLBC[3]
2
RAU2DLBC[2]
1
RAU2DLBC[1]
0
RARECEIVE
PORT B HEC
THRESHOLDU2
DLBC[0]
Software Lock: No
Reset Value: 0x00
The Receive Port A Up2Down Loopback Cell Count register counts the number of incoming loopback cells
detected from the Port A LVDS interface when Up2Down loopback is enabled with the U2DLB bit of the ALBC
register, see ATM AND LVDS LOOPBACK CONTROL—0x1A ALBC. Note that this counter is incremented when
an incoming loopback cell is received and that this differs from the functionality of the Down2Up Loopback Cell
Count register, see ATM DOWN2UP LOOPBACK CELL COUNT—0xE0 D2ULBCC.
• RAU2DLBC[7:0] Port A Up2Down Loopback Cell Count value. This register will not roll-over from 0x00 to
0xFF but will stick at 0xFF.
RECEIVE PORT A CELL DELINEATION THRESHOLDS—0x40 RACDT
Table 55. RACDT
7
ALPHA[3]
Type: Read/Write
6
ALPHA[2]
5
ALPHA[1]
4
ALPHA[0]
3
DELTA[3]
2
DELTA[2]
1
DELTA[1]
0
DELTA[0]
Software Lock: Yes
Reset Value: 0x78
The Receive Port A Cell and Transport Container Delineation Thresholds register controls the operation of the
Port A cell delineation state machine. The cell delineation lock status is reflected in the RALTCLL bit of the RALA
register.
• ALPHA[3:0] When in lock this is the number of consecutive incorrect cell HEC’s required to lose cell
delineation lock.
• DELTA[3:0] When out of lock this is the number of consecutive correct cell HEC’s required to gain cell
delineation lock.
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