DS92UT16 Datasheet, PDF (55/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

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GENERAL CONTROL AND STATUS—0x03 GCS
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
Table 22. GCS
7
6
5
Reserved Reserved
GIE
Type: Bits[5:2] Read/Write
Bit[1:0] Read Only
4
3
2
LT
RESET
CTI
1
0
TIS
SLOCK
Software Lock: Yes
Reset Value: 0x05
• GIE The Global Interrupt Enable enables the device interrupt output pin CPU_INT. Set = Interrupts enabled
and Clear = Interrupts disabled.
• LT The Loop Timing bit enables the connection of the Active Rx port recovered clock to the LVDS Transmit
clock (the active Rx port is as defined by the LBA bit of the LKSC register). LT Set = LVDS Tx clock sourced
from Active Rx port recovered clock. LT Clear = LVDS Tx clock sourced from LVDS_TxClk pin.
• RESET Set = Software reset of all registers except this bit. The Software Lock status as refiected by SLOCK
is also not affected by a software reset.
• CTI Configuration Traffic Inhibit. The setting of this bit initiates the Traffic Inhibit functionality, which stops
traffic flow. The UTOPIA interface will stop transmitting and receiving cells, the LVDS transmit section will
transmit Idle cells and the incoming cells on the active LVDS receive port will be discarded. The MTB and FIB
queues must also be flushed. This bit should be set by the processor whenever the device is being
fundamentally reconfigured from the default settings, specifically whenever any of the PDUCFG, UCFG,
USPAL or USPAM registers are being changed. The processor should set this bit before changing any of the
above mentioned register settings. This will initiate Traffic Inhibit. The TIS bit should then be polled until set to
confirm that traffic is inhibited. Note that the MTB and FIB queues MUST be flushed at this stage. This is
accomplished with the FIBFL and MTBFL bits of the QFL register described in QUEUE FLUSH—0xD8
QFL. The device can now be safely reconfigured. When the TIS bit is set, then traffic is inhibited and the
device can safely be reconfigured. When configuration is completed, then the CTI bit can be cleared by the
processor and normal operation resumed. Note that CTI is set on reset so the device is in Traffic Inhibit
mode. See Configuration and Traffic Inhibit Operation.
• TIS Traffic Inhibit Status. This bit reflects the status of the Traffic Inhibit functionality. When set then traffic is
inhibited as described for the CTI bit above. When clear then the device operates normally. The setting of the
CTI bit will initiate Traffic Inhibit which sets the TIS bit. Clearing of the CTI bit clears the TIS bit.
• SLOCK This refiects the status of the Software Lock functionality. Set = Software lock ON and Clear =
Software Lock OFF. The processor can use this bit to determine the Software Lock functionality status when
writing to lockable registers.
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