DS92UT16 Datasheet, PDF (82/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
OBSOLETE
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
UTOPIA CONFIGURATION—0xA0 UCFG
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Table 78. UCFG
7
Reserved
Type: Read/Write
6
Reserved
5
CLVM[1]
4
CLVM[0]
3
BWIDTH
2
Reserved
1
UBDEN
0
UMODE
Software Lock: Yes
Reset Value: 0x00
The UTOPIA Configuration register defines the UTOPIA interface operating modes. The default is ATM Layer
Level 2 mode (31 ports) using CLAV0 with16 bit data.
• CLVM[1:0] Clav Mode bits. 00 = Up to 31 ports using CLAV0, 01 or 10 = Reserved, 11 = Up to 248 ports
using CLAV0 to CLAV7.
• BWIDTH UTOPIA data bus width. Set = 8-bit data bus and Clear = 16-bit mode.
• UBDEN UTOPIA Bidirectional pins enable. Set = the UTOPIA bidirectional pins take on the functionality as
defined by the UMODE setting. Clear = All UTOPIA interface bidirectional pins are tri-stated. This is to avoid
pin contention at the UTOPIA pins on reset.
• UMODE UTOPIA ATM or PHY mode. Set = PHY Layer interface and Clear = ATM Layer Interface.
UTOPIA CONNECTED PORT LIST—0xA1 to 0xA4 UCPL3 to UCPL0
Table 79. UCPL1–UCPL0
7
UCPL3 0xA1 Reserved
UCPL2 0xA2 UCPL2[7]
UCPL1 0xA3 UCPL1[7]
UCPL0 0xA4 UCPL0[7]
Type: Read/Write
6
UCPL3[6]
UCPL2[6]
UCPL1[6]
UCPL0[6]
5
UCPL3[5]
UCPL2[5]
UCPL1[5]
UCPL0[5]
4
UCPL3[4]
UCPL2[4]
UCPL1[4]
UCPL0[4]
3
UCPL3[3]
UCPL2[3]
UCPL1[3]
UCPL0[3]
2
UCPL3[2]
UCPL2[2]
UCPL1[2]
UCPL0[2]
1
UCPL3[1]
UCPL2[1]
UCPL1[1]
UCPL0[1]
0
UCPL3[0]
UCPL2[0]
UCPL1[0]
UCPL0[0]
Software Lock: Yes
Reset Value: 0xFF, except UCPL3 = 0x7F
The UCPL3, UCPL2, UCPL1 and UCPL0 registers define the connected UTOPIA ports for polling. The sub-ports
present for the connected ports is defined in the UCSPL register. Note that at least one port has to be connected
for correct polling to occur, so these registers should never be set to all zeroes. See UTOPIA Interface
Operation. If no ports are required then use of the Configuration Traffic inhibit functionality is recommended. See
Configuration and Traffic Inhibit Operation.
• UCPL3–UCPL0 UCPL3[6] corresponds to port 31 and UCPL0[0] corresponds to port 0. When a bit is set then
the port is connected and will be polled, when clear the port is not connected and will not be polled.
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